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Power Management

BCM43907 Preliminary Data Sheet

BROADCOM CONFIDENTIAL

Broadcom®

March 12, 2016 • 43907-DS104-R

Page 20

Figure 4: Typical Power Topology (Page 2 of 2)

Power Management

The BCM43907 has been designed with the stringent power consumption requirements of mobile devices in

mind. All areas of the chip design are optimized to minimize power consumption. Silicon processes and cell

libraries were chosen to reduce leakage current and supply voltages. Additionally, the BCM43907 includes an

advanced Power Management Unit (PMU) sequencer. The PMU sequencer provides significant power savings

by putting the BCM43907 into various power management states appropriate to the environment and activities

that are being performed. The power management unit enables and disables internal regulators, switches, and

other blocks based on a computation of the required resources and a table that describes the relationship

between resources and the time needed to enable and disable them. Power-up sequences are fully

programmable. Configurable, free-running counters (running at a 32.768 kHz LPO clock) in the PMU sequencer

are used to turn on and turn off individual regulators and power switches. Clock speeds are dynamically

changed (or gated altogether) as a function of the mode. Slower clock speeds are used whenever possible.

Table 1 provides descriptions for the BCM43907 power modes.

VBAT

LDO3P3

BCM43907 2.5V and 3.3V

WLRF PA(2.4 GHz and 5 GHz)

WLRF Pad (2.4 GHz and 5 GHz)

VDDIO_RF

WL OTP 3.3V

2.5V Cap-less

LNLDO

2.5V Cap-less

LNLDO

2.5V Cap-less

LNLDO

Inside WL Radio

3.3V

VCOLDO2P5

WL RF RX, TX, NMOS, Mini-PMU LDOs

WL RF VCO

WL RF CP

2.5V

450 to

800 mA

Supply ball

Supply bump/pad

Ground ball

Ground bump/pad

External to chip

Power

switch

No power switch

No dedicated power switch, but internal power-

down modes and block-specific power switches

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