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FM3808 Datasheet(PDF) 21 Page - Ramtron International Corporation |
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FM3808 Datasheet(HTML) 21 Page - Ramtron International Corporation |
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21 / 28 page ![]() FM3808 Rev 1.1 May 2003 Page 21 of 28 Read Cycle AC Parameters (TA = -40° C to + 85° C, VDD = 4.5V to 5.5V unless otherwise specified) Symbol Parameter Min Max Units Notes tCE Chip Enable Access Time ( to data valid) 70 ns tCA Chip Enable Active Time 70 2,000 ns tRC Read Cycle Time 130 ns tPC Precharge Time 60 ns tAS Address Setup Time 0 ns tAH Address Hold Time 10 ns tOE Output Enable Access Time 10 ns tHZ Chip Enable to Output High-Z 15 ns 1 tOHZ Output Enable to Output High-Z 15 ns 1 Write Cycle AC Parameters (TA = -40° C to + 85° C, VDD = 4.5V to 5.5V unless otherwise specified) Symbol Parameter Min Max Units Notes tCA Chip Enable Active Time 70 2,000 ns tCW Chip Enable to Write High 70 ns tWC Write Cycle Time 130 ns tPC Precharge Time 60 ns tAS Address Setup Time 0 ns tAH Address Hold Time 10 ns tWP Write Enable Pulse Width 30 ns tDS Data Setup 30 ns tDH Data Hold 5 ns tWZ Write Enable Low to Output High Z 15 ns 1 tWX Write Enable High to Output Driven 10 ns 1 tHZ Chip Enable to Output High-Z 15 ns 1 tWS Write Setup 0 ns 2 tWH Write Hold 0 ns 2 Notes 1 This parameter is periodically sampled and not 100% tested. 2 The relationship between /CE and /WE determines if a /CE- or /WE-controlled write occurs. There is no timing specification associated with this relationship. Power Cycle Timing (TA = -40° C to + 85° C) Symbol Parameter Min Max Units Notes tINT INT signal active after VTP 100 ns 1,2 tPD Last Access Complete to VLO 0 ns 1,3 tRI VLO to inputs recognized on power-up 1 µs 1,4 tR Rise time of VDD from VBG to VLO 100 µs 1,5 tF Fall time of VDD from VLO to VBG 100 µs 1,5 Notes 1 This parameter is periodically sampled and not 100% tested. 2 If power monitor is programmed to generate INT. 3 Access is blocked at VLO. The last access should be complete prior to reaching VLO. The early warning power fail interrupt may be useful in accomplishing this. 4 Failing to satisfy tRI may result in the first access being ignored. Failure to raise /CE to a logic high prior to VDD>VLO may result in improper operation. 5 Slew rate for proper transition between the locked-out condition and normal operation. |
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