TLF6630

August 1989

DM54L73 Dual Master-Slave J-K Flip-Flops

with Clear and Complementary Outputs

General Description

This device contains two independent positive pulse trig-

gered J-K flip-flops with complementary outputs The J and

K data is processed by the flip-flops after a complete clock

pulse While the clock is low the slave is isolated from the

master On the positive transition of the clock the data from

the J and K inputs is transferred to the master While the

clock is high

the data from the J and K inputs are

disabled On the negative transition of the clock the data

from the master is transferred to the slave The logic states

of the J and K inputs must not be allowed to change while

the clock is high Data is transferred to the outputs on the

falling edge of the clock pulse A low logic level on the clear

input will reset the outputs regardless of the logic states of

the other inputs

Connection Diagram

Dual-In-Line Package

TLF6630 – 1

Order Number DM54L73J or DM54L73W

See NS Package Number J14A or W14B

Function Table

Inputs

Outputs

CLR

CLK

J

K

Q

Q

LX

X

X

L

H

H

LL

H

HL

H

L

H

LH

L

H

H

H

H

Toggle

e

Positive pulse data The J and K inputs must be held constant while

the clock is high Data is transferred to the outputs on the falling edge of the

clock pulse

established

each complete high level clock pulse

C1995 National Semiconductor Corporation

RRD-B30M105Printed in U S A