5

Revision A

EQSEL

17(14)

3-Level Se-

lect

Equalization Select: This three level Equalization Select input controls the

mode

of

receiver

equalization.

Forcing

a

median

voltage

level,

accomplished by allowing EQSEL to float, selects the adaptive

equalization mode which automatically regulates the equalization effects

based on signal degradation caused by the media. The other two levels are

intended as test modes and are not a guaranteed mode of operation.

Forcing a voltage less than 1.5V, selects full equalization which provides

fixed equalization for a maximum length of cable. Forcing a voltage greater

than 3.0V turns the receive equalizer off.

CDET

18(15)

CMOS In Cable Detect Bar: The active low Cable Detect CMOS input is provided to

support the option of external Cable Detection circuitry (wire fault). With

CDET low, the transceiver functions normally. With CDET high, the signal

detect output is forced low which inhibits data reception by the PHY and

the PMID outputs are forced to ECL static levels. The exception is in the

case of Loopback when the Signal Detect output is forced high regardless

of all other conditions. Please refer to the National Semiconductor Com-

mon Magnetics application note for further detail regarding the proper use

of the DP83223 in a 10/100 Ethernet application.

Symbol

Pin No

PLCC(PQFP)

Type

Description