11

DAC7616

SBAS186

SYMBOL

DESCRIPTION

MIN

TYP

MAX

UNITS

Data Valid to CLK Rising

25

ns

Data Held Valid after CLK Rises

20

ns

CLK HIGH

30

ns

CLK LOW

50

ns

CS LOW to CLK Rising

55

ns

CLK HIGH to CS Rising

15

ns

LDAC HIGH to CLK Rising

40

ns

CLK Rising to LDAC LOW

15

ns

LDAC LOW Time

45

ns

RESETSEL Valid to RESET LOW

25

ns

RESET LOW Time

70

ns

Settling Time

10

µs

DIGITAL INTERFACE

Figure 2 and Table I provide the basic timing for the

DAC7616. The interface consists of a serial clock (CLK),

serial data (SDI), and a load DAC signal (LDAC). In

addition, a chip select (CS) input is available to enable serial

communication when there are multiple serial devices. An

asynchronous reset input (RESET) is provided to simplify

start-up conditions, periodic resets, or emergency resets to a

known state.

FIGURE 2. DAC7616 Timing.

The DAC code and address are provided via a 16-bit serial

interface as shown in Figure 2. The first two bits select the

DAC register that will be updated when LDAC goes LOW

(see Table II). The next two bits are not used. The last 12 bits

is the DAC code which is provided, most significant bit first.

Note that CS and CLK are combined with an OR gate,

whose output controls the serial-to-parallel shift register

internal to the DAC7616 (see the block diagram on the front

of this data sheet). These two inputs are completely inter-

changeable. In addition, care must be taken with the state of

CLK when CS rises at the end of a serial transfer. If CLK is

LOW when CS rises, the OR gate will provide a rising edge

to the shift register, shifting the internal data one additional

bit. The result will be incorrect data and possible selection of

the wrong DAC.

A1

(MSB)

(LSB)

SDI

CLK

CS

LDAC

A0

X

X

D11

D10

D9

D3

D2

D1

D0

SDI

CLK

LDAC

RESET

V

OUT

tcss

t

LD1

t

CL

t

CH

t

DS

t

DH

t

LD2

t

LDDW

t

LDDW

t

S

t

RSTW

t

RSSH

t

CSH

t

S

1 LSB

ERROR BAND

1 LSB

ERROR BAND

RESETSEL

STATE OF

SELECTED

SELECTED

DAC

DAC

A1

A0

LDAC

RESET

REGISTER

REGISTER

L

L

H

A

Transparent

L

H

L

H

B

Transparent

H

L

L

H

C

Transparent

H

H

L

H

D

Transparent

X

H

H

NONE

(All Latched)

X

X

X

L

ALL

NOTES: (1) L = Logic LOW. (2) X = Don’t Care. (3) Resets to either 000H or

rises, all registers that are in their latched state retain the reset value.

TABLE II. Control Logic Truth Table.