74ALVC74 datasheet(4/20 Pages) PHILIPS

4 / 20 page

2003 May 26

Philips Semiconductors

Product speciﬁcation

Dual D-type ﬂip-ﬂop with set and reset;

positive-edge trigger

74ALVC74

PINNING

SYMBOL

DESCRIPTION

11RD

asynchronous reset-direct input

(active LOW)

data input

1CP

clock input (LOW-to-HIGH,

edge-triggered)

41SD

asynchronous set-direct input

(active LOW)

true ﬂip-ﬂop output

61Q

complement ﬂip-ﬂop output

GND

ground (0 V)

82Q

complement ﬂip-ﬂop output

true ﬂip-ﬂop output

2SD

asynchronous set-direct input

(active LOW)

2CP

clock input (LOW-to-HIGH,

edge-triggered)

data input

2RD

asynchronous reset-direct input

(active LOW)

VCC

supply voltage

Fig.1 Pin configuration SO14 and TSSOP14.

handbook, halfpage

MNA417

1RD

1CP

1SD

GND

2SD

2CP

2RD

VCC

Fig.2 Pin configuration DHVQFN14.

handbook, halfpage

114

1RD

VCC

1CP

1SD

2RD

2CP

2SD

GND

GND(1)

Top view

MDB105

(1) The die substrate is attached to this pad using conductive die

attach material. It can not be used as a supply pin or input.

Fig.3 Logic symbol.

MNA418

handbook, halfpage

410

1SD

2CP

1CP

2SD

113

1RD 2RD

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