AD5253/AD5254

Rev. 0 | Page 15 of 28

From Master to Slave

From Slave to Master

S = Start Condition.

P = Stop Condition.

A = Acknowledge (SDA Low).

A = Not Acknowledge (SDA High).

R/W= Read Enable Bit, Logic High/Write Enable Bit, Logic Low.

CMD/REG = Command Enable Bit, Logic High/Register Access Bit, Logic Low.

EE/RDAC = EEMEM Register, Logic High/RDAC Register, Logic Low.

A4, A3, A2, A1, A0 = RDAC/EEMEM Register Addresses.

0 WRITE

S

0

1

0

1

1

A

D

1

A

D

0

0

A

A

4

A

3

A

2

A

1

A

0

A

P

DATA

0

(1 BYTE +

ACKNOWLEDGE)

SLAVE ADDRESS

INSTRUCTIONS

AND ADDRESS

CMD/

REG

EE/

RDAC

0 REG

A/

A

Figure 27. Single Write Mode

0 WRITE

S

0

1

0

1

1

A

D

1

A

D

0

0

A

A

4

A

3

A

2

A

1

A

0

P

A

A

RDAC_N

DATA

RDAC_N + 1

DATA

0

(N BYTE +

ACKNOWLEDGE)

SLAVE ADDRESS

INSTRUCTIONS

AND ADDRESS

CMD/

REG

EE/

RDAC

0 REG

A/

A

Figure 28. Consecutive Write Mode

Table 6. Addresses for Writing Data Byte Contents to RDAC Registers (R/W = 0, CMD/REG = 0, EE/RDAC = 0)

A4

A3

A2

A1

A0

RDAC

Data Byte Description

0

0

0

0

0

RDAC0

6-/8-bit wiper setting (2 MSBs of AD5253 are X)

0

0

0

0

1

RDAC1

6-/8-bit wiper setting (2 MSBs of AD5253 are X)

0

0

0

1

0

RDAC2

6-/8-bit wiper setting (2 MSBs of AD5253 are X)

0

0

0

1

1

RDAC3

6-/8-bit wiper setting (2 MSBs of AD5253 are X)

0

0

1

0

0

Reserved

:

:

:

:

:

0

1

1

1

1

Reserved