AD7997 datasheet(15/32 Pages) AD

15 / 32 page

AD7997/AD7998

Rev. 0 | Page 15 of 32

CIRCUIT INFORMATION

The AD7997/AD7998 are low power, 10- and 12-bit, single-

supply, 8-channel A/D converters. The parts can be operated

from a 2.7 V to 5.5 V supply.

The AD7997/AD7998 have an 8-channel multiplexer, an on-

chip track-and-hold, an A/D converter, an on-chip oscillator,

internal data registers, and an I2C-compatible serial interface, all

housed in a 20-lead TSSOP. This package offers considerable

space-saving advantages over alternative solutions. The

AD7997/AD7998 require an external reference in the range of

1.2 V to VDD.

The AD7997/AD7998 typically remain in a power-down state

while not converting. When supplies are first applied, the parts

come up in a power-down state. Power-up is initiated prior to

a conversion, and the device returns to shutdown when the

conversion is complete. Conversions can be initiated on the

AD7997/AD7998 by pulsing the CONVST signal, using an

automatic cycle interval mode, or a command mode where

wake-up and a conversion occur during a write address

function (see the Modes of Operation section). When the

conversion is complete, the AD7997/AD7998 again enter

shutdown mode. This automatic shutdown feature allows power

saving between conversions. This means any read or write

operation across the I2C interface can occur while the device is

in shutdown.

CONVERTER OPERATION

The AD7997/AD7998 are successive approximation analog-to-

digital converters based around a capacitive DAC. Figure 18

and Figure 19 show simplified schematics of the ADC during

the acquisition and conversion phase, respectively. Figure 18

shows the acquisition phase. SW2 is closed and SW1 is in

position A, the comparator is held in a balanced condition,

and the sampling capacitor acquires the signal on VIN.

CAPACITIVE

DAC

VIN

COMPARATOR

CONTROL

LOGIC

SW1

SW2

AGND

Figure 18. ADC Acquisition Phase

At the beginning of a conversion, SW2 opens and SW1 moves

to position B, causing the comparator to become unbalanced, as

shown in Figure 19. The input is disconnected once the con-

version begins. The control logic and the capacitive DAC are

used to add and subtract fixed amounts of charge from the

sampling capacitor to bring the comparator back into a

balanced condition. When the comparator is rebalanced, the

conversion is complete. The control logic generates the ADC

output code. Figure 20 shows the ADC transfer characteristic.

VIN

COMPARATOR

CONTROL

LOGIC

SW1

SW2

AGND

CAPACITIVE

DAC

Figure 19. ADC Conversion Phase

ADC Transfer Function

The output coding of the AD7997/AD7998 is straight binary.

The designed code transitions occur at successive integer LSB

values (1 LSB, 2 LSB, and so on). The LSB size is REFIN/1024 for

the AD7997 and REFIN/4096 for the AD7998. Figure 20 shows

the ideal transfer characteristic for the AD7997/AD7998.

000...000

ANALOG INPUT

0V TO REFIN

111...111

000...001

000...010

111...110

111...000

011...111

AGND + 1LSB

+REFIN – 1LSB

AD7998 1LSB = REFIN/4096

AD7997 1LSB = REFIN/1024

Figure 20. AD7997/AD7998 Transfer Characteristic

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