AD9864BCPZRL datasheet(23/44 Pages) AD

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AD9864

Rev. 0 | Page 23 of 44

POWER CONTROL

To allow power consumption to be minimized, the AD9864

possesses numerous SPI programmable power-down and bias

control bits. The AD9864 powers up with all of its functional

blocks placed into a standby state, i.e., STBY register default is

0xFF. Each major block may then be powered up by writing a 0

to the appropriate bit of the STBY register. This scheme pro-

vides the greatest flexibility for configuring the IC to a specific

application as well as for tailoring the IC’s power-down and

wake-up characteristics. Table 11 summarizes the function of

each of the STBY bits. Note that when all the blocks are in

standby, the master reference circuit is also put into standby,

and thus the current is reduced further by 0.4 mA.

Table 11. Standby Control Bits

STBY Bit

Effect

Current

Reduction

(mA)1

Wake-Up

Time (ms)

7: REF

Voltage reference OFF;

all biasing shut down.

0.6

<0.1 (CREF

= 4.7 nF)

6: LO

LO synthesizer OFF,

IOUTL three-state.

1.2

Note 2

5: CKO

Clock oscillator OFF.

1.1

Note 2

4: CK

Clock synthesizer OFF,

IOUTC three-state. Clock

buffer OFF if ADC is OFF.

1.3

Note 2

3: GC

Gain control DAC OFF.

GCP and GCN three-

state.

0.2

Depends

on CGC

2: LNAMX

LNA and Mizer OFF.

CXVM, CXVL, and CXIF

three-state.

8.2

<2.2

1: Unused

0: ADC

ADC OFF; Clock buffer

OFF if CLK synthesizer

OFF; VCM three-state;

clock to the digital filter

halted; digital outputs

static.

9.2

<0.1

NOTES

1When all blocks are in standby, the master reference circuit is also put into

standby, and thus the current is further reduced by 0.4 mA.

2Wake-up time is dependent on programming and/or external components.

LO SYNTHESIZER

The LO synthesizer shown in Figure 38 is a fully programmable

phase-locked loop (PLL) capable of 6.25 kHz resolution at

input frequencies up to 300 MHz and reference clocks of up to

25 MHz. It consists of a low noise digital phase-frequency

detector (PFD), a variable output current charge pump (CP), a

14-bit reference divider, programmable A and B counters, and

a dual-modulus 8/9 prescaler.

The A (3-bit) and B (13-bit) counters, in conjunction with the

dual 8/9 modulus prescaler, implement an N divider with N = 8

× B + A. In addition, the 14-bit reference counter (R Counter)

allows selectable input reference frequencies, fREF, at the PFD

input. A complete PLL can be implemented if the synthesizer is used

with an external loop filter and voltage controlled oscillator (VCO).

The A, B, and R counters can be programmed via the following

registers: LOA, LOB, and LOR. The charge pump output

current is programmable via the LOI register from 0.625 mA to

5.0 mA using the equation

(

)

LOI

IPUMP

625

1 ×

(2)

An on-chip fast acquire function (enabled by the LOF bit)

automatically increases the output current for faster settling

during channel changes. The synthesizer may also be disabled

using the LO standby bit located in the STBY register.

fREF

fLO

FROM

VCO

REF

BUFFER

÷R

PHASE/

FREQUENCY

DETECTOR

FAST

ACQUIRE

CHARGE

PUMP

TO EXTERNAL

LOOP

FILTER

BUFFER

÷8/9

A. B

COUNTERS

LOR

LOA, LOB

Figure 38. LO Synthesizer

The LO (and CLK) synthesizer works in the following manner.

The externally supplied reference frequency, fREF, is buffered

and divided by the value held in the R counter. The internal fREF

is then compared to a divided version of the VCO frequency,

fLO. The phase/frequency detector provides UP and DOWN

pulses whose widths vary, depending upon the difference in

phase and frequency of the detector’s input signals. The

UP/DOWN pulses control the charge pump, making current

available to charge the external low-pass loop filter when there

is a discrepancy between the inputs of the PFD. The output of

the low-pass filter feeds an external VCO whose output fre-

quency, fLO, is driven such that its divided down version, fLO,

matches that of fREF, thus closing the feedback loop.

The synthesized frequency is related to the reference frequency

and the LO register contents as follows:

(

)

REF

LOR

LOA

LOB

(3)

Note that the minimum allowable value in the LOB register is 3

and its value must always be greater than that loaded into LOA.

An example may help illustrate how the values of LOA, LOB, and

LOR can be selected. Consider an application employing a 13

MHz crystal oscillator, i.e., fREF = 13 MHz, with the requirement

that fREF = 100 kHz and fLO = 143 MHz, i.e., high side injection

with fIF = 140.75 MHz and fCLK = 18 MSPS. LOR is selected to be

130 such that fREF = 100 kHz. The N-divider factor is 1430, which

can be realized by selecting LOB = 178 and LOA = 6.

AD9864BCPZRL Datasheet(PDF) 23 Page - Analog Devices

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