DP83907VF datasheet(47/70 Pages) NSC

47 / 70 page

60 Operation of DP83907 (Continued)

Conditions Required to Begin Transmission

In order to transmit a packet the following three conditions

must be met

1 The Interframe Gap Timer has timed out the first 64 ms

of the Interframe Gap

2 At least one byte has entered the FlFO (This indicates

that the burst transfer has been started)

3 If a collision had been detected then before transmission

the packet time must have timed out

In typical systems the DP83907 prefetches the first burst of

bytes before the 64 ms timer expires The time during which

DP83907 transmits preamble can also be used to load the

FIFO

Note

If carrier sense is asserted before a byte has been loaded into the

FIFO the DP83907 will become a receiver

Collision Recovery

During transmission the Buffer Management logic monitors

the transmit circuitry to determine if a collision has occurred

If a collision is detected the Buffer Management logic will

reset the FlFO and restore the Transmit DMA pointers for

retransmission of the packet The COL bit will be set in the

TSR and the NCR (Number of Collisions Register) will be

incremented If 15 retransmissions each result in a collision

the transmission will be aborted and the ABT bit in the TSR

will be set

Note

NCR reads as zeroes if excessive collisions are encountered

Transmit Packet Assembly Format

The following diagrams describe the format for how packets

must be assembled prior to transmission for different byte

ordering schemes The various formats are selected in the

Data Configuration Register

D15

Destination Address 1

Destination Address 0

Destination Address 3

Destination Address 2

Destination Address 5

Destination Address 4

Source Address 1

Source Address 0

Source Address 3

Source Address 2

Source Address 5

Source Address 4

TypeLength 1

Type Length 0

Data 1

Data 0

BOS e 0 WTS e 1 in Data Configuration Register

This format is used with Series 32xxx or 808xx processors

D15

Destination Address 0

Destination Address 1

Destination Address 2

Destination Address 3

Destination Address 4

Destination Address 5

Source Address 0

Source Address 1

Source Address 2

Source Address 3

Source Address 4

Source Address 5

Type Length 0

TypeLength 1

Data 0

Data 1

BOS e 1 WTS e 1 in Data Configuration Register

This format is used with 680x0 type processors

Destination Address 0

Destination Address 1

Destination Address 2

Destination Address 3

Destination Address 4

Destination Address 5

Source Address 0

Source Address 1

Source Address 2

Source Address 3

Source Address 4

Source Address 5

BOS e 0 WTS e 0 in Data Configuration Register

This format is used with general 8 bit processors

Note

All examples above will result in a transmission of a packet in order of

DA0 DA1 DA3

bits within each byte will be transmitted least signifi-

cant bit first

DA e Destination Address

DP83907VF Datasheet(PDF) 47 Page - National Semiconductor (TI)

DP83907VF Datasheet(HTML) 47 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70

Datasheet Download

Link URL