ADS7828

12

SBAS181B

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FIGURE 4. Typical Read Sequence in HS Mode.

NOTE: (A) Use repeated START to remain in HS mode instead of STOP.

Sr

A1

10

010

A0

RA

Read-AddressingByte

From master to slave

From slave to master

ADC Converting Mode

W = 0 (WRITE)

R = 1 (READ)

SX

00

001

X

X

N

F/S Mode

HS Mode Master Code

Sr

A1

10

010

A0

W

ASD

C2 C1 C0 PD1 PD0 XXA

Write-Addressing Byte

Command Byte

ADC Sampling Mode

HS Mode Enabled

ADC Power-Down Mode

HS Mode Enabled

000

0

D11 D10 D9 D8 AD7 D6 . . .D1 D0

NP

2

×(8 bits + ack/not-ack)

ADC Power-Down Mode

(Depends on Power-Down Selection Bits)

HS Mode Enabled

Return to F/S Mode (see Note A)

SCLH is stretched LOW for waiting the data converted

A = acknowledge (SDA Low)

N = not-acknowledge (SDA High)

S = START Condition

P = STOP Condition

Sr = repeated START Condition