ADV611/ADV612

–12–

REV. 0

[5]

FIFO Stop, FIFOSTP. This condition indicates that the FIFO is full in decode mode and empty in encode mode. In

decode mode only, FIFOSTP status actually behaves more conservatively than this. In decode mode, even when FIFOSTP

is indicated, there are still 32 empty Dwords available in the FIFO and 32 more Dword writes can safely be performed.

This status bit indicates the following:

0

No FIFO Stop condition, reset value (FIFO_STP pin LO)

1

FIFO empty (encode) or full (decode) (FIFO_STP pin HI)

[6]

Memory Error, MERR. This condition indicates that an error has occurred at the DRAM memory interface. This condition can

be caused by a defective DRAM, the inability of the Host to keep up with the ADV611/ADV612 compressed data stream, or bit

errors in the data stream. Note that the ADV611/ADV612 recovers from this condition without host intervention.

0

No memory error condition, reset value

1

Memory error

[7]

Reserved (always read/write zero)

[8]

Interrupt Enable on CCIRER, IE_CCIRER. This mask bit selects the following:

0

Disable CCIR-656 data error interrupt, reset value

1

Enable interrupt on error in CCIR-656 data

[9]

Interrupt Enable on STATR, IE_STATR. This mask bit selects the following:

0

Disable Statistics Ready interrupt, reset value

1

Enable interrupt on Statistics Ready

[10]

Interrupt Enable on LCODE, IE_LCODE. This mask bit selects the following:

0

Disable Last Code Read interrupt, reset value

1

Enable interrupt on Last Code Read from FIFO

[11]

Interrupt Enable on FIFOSRQ, IE_FIFOSRQ. This mask bit selects the following:

0

Disable FIFO Service Request interrupt, reset value

1

Enable interrupt on FIFO Service Request

[12]

Interrupt Enable on FIFOERR, IE_FIFOERR. This mask bit selects the following:

0

Disable FIFO Stop interrupt, reset value

1

Enable interrupt on FIFO Stop

[13]

Interrupt Enable on FIFOSTP, IE_FIFOSTP. This mask bit selects the following:

0

Disable FIFO Error interrupt, reset value

1

Enable interrupt on FIFO Error

[14]

Interrupt Enable on MERR, IE_MERR. This mask bit selects the following:

0

Disable memory error interrupt, reset value

1

Enable interrupt on memory error

[15]

Reserved (always read/write zero)

Mode Control Register

Indirect (Read/Write) Register Index 0x00

This register holds configuration data for the ADV611/ADV612’s video interface format and controls several other video interface

features. For more information on formats and modes, see the Video Interface section. Bits in this register have the following functions:

[3:0]

Video Interface Format, VIF[3:0]. These bits select the interface format. Valid settings include the following (all

other values are reserved):

0x0

CCIR-656, reset value

0x2

MLTPX (Philips)

[4]

VCLK Output Divided by two, VCLK2. This bit controls the following:

0

Do not divide VCLK output (VCLKO = VCLK), reset value

1

Divide VCLK output by two (VCLKO = VCLK/2)

[5]

Video Interface Master/Slave Mode Select, M/S. This bit selects the following:

0

Slave mode video interface (External control of video timing, HSYNC-VSYNC-FIELD are inputs), reset value

1

Master mode video interface (ADV611/ADV612 controls video timing, HSYNC-VSYNC are outputs)

[6]

Video Interface 525/625 (NTSC/PAL) Mode Select, P/N. This bit selects the following:

0

525 mode video interface, reset value

1

625 mode video interface