Philips Semiconductors

Product data

SA8028

2.5 GHz sigma delta fractional-N /

760 MHz IF integer frequency synthesizers

2002 Feb 22

18

2.5.3

Programming the Lock Detect <C4:C5>

Lock detection is available only for the RF and IF phase detector. A ‘0’ in bit <C4:C5> is used for TTL, while a ‘1’ in bit <C4:C5> is used for RTL.

Table 13. Lock detect select

L1

L0

Select

0

0

0

1

RF/IF (open drain)

1

0

RF (push/pull)

1

1

IF (push/pull)

NOTE:

1. Combined RF_IF lock detect signal present at the lock pin (push/pull).

2.5.4

Programming the Charge Pump Gain <C7:C6>

The RF phase detector drives the charge pumps on the PHP and PHI pins, while the IF phase detector drives the charge pump on the PHA pin.

programmed by the CP0, CP1 bits in the C–word, as seen in Table 1. For more information on charge pump speed-up mode, refer to section

1.6.

2.5.5

Programming the IF Divider for the IF Loop <C21:C8>

The divider is a fully programmable counter. The allowable divide ratios, A, are from 128 to 16383, bits <C21:C8>. Table 14 shows all the

possible values that can be programmed into the C-word for the IF divider.

Table 14. Allowable Values (A) for the IF Divider

C21

C20

C19

C18

C17

C16

C15

C14

C13

C12

C11

C10

C9

C8

A

0

0

0

0

0

0

1

0

0

0

0

0

0

0

128

0

0

0

0

0

0

1

0

0

0

0

0

0

1

129

0

0

0

0

0

0

1

0

0

0

0

0

1

0

130

—

—

—

—

—

—

—

—

—

—

—

—

—

—

…

1

1

1

1

1

1

1

1

1

1

1

1

1

0

16382

1

1

1

1

1

1

1

1

1

1

1

1

1

1

16383

2.6

D-word Register

The D-word is for test purposes only. All bits in this test word should be initialized to 0 for normal operation. When initially applying or

re-applying power to the chip, an internal power-up reset pulse if generated which sets the programming-words to their default values and which

resets the sigma-delta modulator to its “all-0” state. It is also recommended that the D-word be manually reset to all zeros, following initial

power-up, to avoid unknown states.

Table 15. D-word, length 24 bits

Last IN

<21>

<20>

<19>

<18>

<17>

<16>

<15>

<14>

<13>

<12>

<11>

<10>

<9>

<8>

<7>

<6>

<5>

<4>

<3>

<2>

<1>

<0>

Address

Synthesizer Test bits

1

1

0

–

–

–

–

Tdis-spu

Tspu

–

–

–

TreadN

–

–

–

–

–

–

–

–

–

–

–

Default

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

D word address

Fixed to 110.

Tdis-spu

Speed-up mode disabled.

NOTE: All other test bits must be set to 0 for normal operation.

Tspu: Speed up

Speed-up mode always on.

NOTE: All other test bits must be set to 0 for normal operation.

TreadN

Used to “request to read” bit settings from bits <B21:12>. For more information on reading out the N value,

refer to Section 2.0, Serial Programming Bus.