PGATE

GND

Internal

Regulator

Level

Shift

en

Band Gap

Reference

Soft-Start

Vref Ramp

+

-

+

-

Current

Bias

reset

Blanking

Timer

UVD-Disable

UVD-Disable

en

reset

FB

EN

UVD

Comp

Hysteretic

Comp

LM3475

SNVS239C – OCTOBER 2004 – REVISED OCTOBER 2015

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7 Detailed Description

7.1 Overview

The LM3475 is a buck (step-down) DC-DC controller that uses a hysteretic control architecture, which results in

Pulse Frequency Modulated (PFM) regulation. The hysteretic control scheme does not utilize an internal

oscillator. Switching frequency depends on external components and operating conditions. Operating frequency

decreases at light loads, resulting in excellent efficiency compared to PWM architectures. Because switching is

directly controlled by the output conditions, hysteretic control provides exceptional load transient response.

7.2 Functional Block Diagram

7.3 Feature Description

7.3.1 Hysteretic Control Circuit

The LM3475 uses a comparator-based voltage control loop. The voltage on the feedback pin is compared to a

0.8V reference with 21mV of hysteresis. When the FB input to the comparator falls below the reference voltage,

the output of the comparator goes low. This results in the driver output, PGATE, pulling the gate of the PFET low

and turning on the PFET.

inductor. Current through the inductor ramps up linearly, and the output voltage increases. As the FB voltage

reaches the upper threshold (reference voltage plus hysteresis) the output of the comparator goes high, and the

PGATE turns the PFET off. When the PFET turns off, the catch diode turns on, and the current through the

inductor ramps down. As the output voltage falls below the reference voltage, the cycle repeats. The resulting

output, inductor current, and switch node waveforms are shown in Figure 9.

8

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