SC28L91 datasheet(25/42 Pages) PHILIPS

25 / 42 page

Philips Semiconductors

Product specification

SC28L91

3.3V–5.0V Universal Asynchronous

Receiver/Transmitter (UART)

2000 Sep 22

6. The last character will be transmitted and OPR[0] will be reset

one bit time after the last stop bit, causing RTSN to be negated.

MR2[4]— Clear-to-Send Control

If this bit is 0, CTSN has no effect on the transmitter. If this bit is a 1,

the transmitter checks the state of CTSN (IP0) the time it is ready to

send a character. If IP0 is asserted (Low), the character is

transmitted. If it is negated (High), the TxD output remains in the

marking state and the transmission is delayed until CTSN goes low.

Changes in CTSN while a character is being transmitted do not

affect the transmission of that character..

MR2[3:0]— Stop Bit Length Select

This field programs the length of the stop bit appended to the

transmitted character. Stop bit lengths of 9/16 to 1 and 1–9/16 to 2

bits, in increments of 1/16 bit, can be programmed for character

lengths of 6, 7, and 8 bits. For a character lengths of 5 bits, 1–1/16

to 2 stop bits can be programmed in increments of 1/16 bit. In all

cases, the receiver only checks for a ‘mark’ condition at the center

of the stop bit position (one half-bit time after the last data bit, or

after the parity bit if enabled is sampled).

If an external 1X clock is used for the transmitter, then MR2[3] = 0

selects one stop bit and MR2[3] = 1 selects two stop bits to be

transmitted.

SC28L91 Datasheet(PDF) 25 Page - NXP Semiconductors