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TMS320C6414 Datasheet(PDF) 13 Page - Texas Instruments |
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TMS320C6414 Datasheet(HTML) 13 Page - Texas Instruments |
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13 / 141 page ![]() TMS320C6414, TMS320C6415, TMS320C6416 FIXED-POINT DIGITAL SIGNAL PROCESSORS SPRS146N − FEBRUARY 2001 − REVISED MAY 2005 13 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 L2 architecture expanded Figure 2 shows the detail of the L2 architecture on the TMS320C6414, TMS320C6415, and TMS320C6416 devices. For more information on the L2MODE bits, see the cache configuration (CCFG) register bit field descriptions in the TMS320C64x Two-Level Internal Memory Reference Guide (literature number SPRU610). 0x0000 0000 011 010 001 111 0x000C 0000 000 L2MODE L2 Memory Block Base Address 0x000F 0000 0x000E 0000 768K-Byte SRAM 128K-Byte RAM 32K-Byte RAM 0x000F FFFF 64K-Byte RAM 32K-Byte RAM 0x000F 8000 Figure 2. TMS320C6414/C6415/C6416 L2 Architecture Memory Configuration |
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