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2015-07-0040

PT0544-2

8/18/15

7

PI4MSD5V9547

8 Channel I2C bus Multiplexer with Reset

Device addressing

Following a START condition the bus master must output the address of the slave it is accessing. The address of

the PI4MSD5V9547 is shown in Figure 4.

The last bit of the slave address defines the operation to be performed. When set to logic 1 a read is selected, while

a logic 0 selects a write operation.

Figure 4:Device address

Control register

Following the successful acknowledgement of the slave address, the bus master sends a byte to the

PI4MSD5V9547 which is stored in the Control register. If multiple bytes are received by the PI4MSD5V9547, it saves

the last byte received. This register can be written and read via the I2C-bus.

Figure 5: Control register

Control register definition

A SCx/SDx downstream pair, or channel, is selected by the contents of the control register. This register is written

after the PI4MSD5V9547 has been addressed. The 4 LSBs of the control byte are used to determine which channel is

to be selected. When a channel is selected, the channel will become active after a STOP condition has been placed on

the I2C-bus. This ensures that all SCx/SDx lines will be in a HIGH state when the channel is made active, so that no

false conditions are generated at the time of connection.