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DS26F31MJ/883 Datasheet(PDF) 3 Page - National Semiconductor (TI) |
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DS26F31MJ/883 Datasheet(HTML) 3 Page - National Semiconductor (TI) |
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3 / 5 page ![]() Test Circuit and Timing Waveforms Note 8: Diagram shown for Enable Low. Switches S1 and S2 open. Note 9: S1 and S2 of Load Circuit are closed except where shown. Note 10: Pulse Generator for all Pulses: Rate ≤ 1.0 MHz, ZO = 50Ω,tr ≤ 6.0 ns, tf ≤ 6.0 ns. Note 11: CL includes probe and jig capacitance. Typical Application DS009614-3 FIGURE 2. AC Load Test Circuit for TRI-STATE Outputs DS009614-4 FIGURE 3. Propagation Delay (Notes 2, 4) DS009614-5 FIGURE 4. Enable and Disable Times (Notes 3, 4) DS009614-6 FIGURE 5. Typical Application www.national.com 3 |
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