TCM8002

DATA PROCESSOR FOR CELLULAR TELEPHONE

SLWS008C − SEPTEMBER 1994 − REVISED JUNE 1996

21

POST OFFICE BOX 655303

POST OFFICE BOX 1443

PRINCIPLES OF OPERATION

address 13 − RX data word 3

This register contains the corrected received data bits 3 −0 and the error-correction status detailed in Table 17.

Table 18. Received Data Word 3

BIT

FUNCTION

7

RX data bit 3

6

RX data bit 2

5

RX data bit 1

4

RX data bit 0

3− 0

Received-data decode status

Table 19. Error-Correction Status

RECEIVED DATA WORD 3

DECODE STATUS

BIT 3

BIT 2

BIT 1

BIT 0

DECODE STATUS

0

0

0

0

No errors detected

0

0

0

1

One error detected in parity bits

0

0

1

0

Two errors detected in parity bits

0

0

1

1

Not used

0

1

0

0

One error corrected in data

0

1

0

1

One error corrected in data, one error detected in parity bits

0

1

1

0

Not used

0

1

1

1

Not used

1

0

0

0

Two errors corrected in data

1

0

0

1

Not used

1

0

1

0

Not used

1

0

1

1

Not used

1

1

0

0

More than two erasures occurred (see Note 2). Up to two data bits

are corrected.

1

1

0

1

More than two erasures occurred (see Note 2). One error detected

in parity bits. Up to one data bit are corrected.

1

1

1

0

More than two erasures occurred (see Note 2). Two errors in parity

bits are detected.

1

1

1

1

More than two errors detected. Data is not corrected.

NOTE 2: A bit erasure occurs when the bit is detected an equal number of times as a 1 and as a 0 over the

valid repeats.