DS21448 datasheet(21/60 Pages) DALLAS

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DS21448 3.3V T1/E1/J1 Quad Line Interface

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CCR3 (02H): Common Control Register 3

(MSB)

(LSB)

TUA1

ATUA1

TAOZ

TPRBSE

TLCE

LIRST

IBPV

IBE

NAME

POSITION

FUNCTION

TUA1

CCR3.7

Transmit Unframed All Ones. The polarity of this bit is set such that the device transmits an all-

ones pattern on power-up or device reset. This bit must be set to 1 to allow the device to transmit

data. The transmission of this data pattern is always timed off JACLK (Figure 1-1).

0 = transmit all ones at TTIP and TRING

1 = transmit data normally

ATUA1

CCR3.6

Automatic Transmit Unframed All Ones. Automatically transmit an unframed all-ones pattern at

TTIP and TRING during an RCL condition.

0 = disabled

1 = enabled

TAOZ

CCR3.5

Transmit Alternate Ones and Zeros. Transmit a …101010… pattern at TTIP and TRING. The

transmission of this data pattern is always timed off TCLK.

0 = disabled

1 = enabled

TPRBSE

CCR3.4

Transmit PRBS Enable. Transmit a 2

15 - 1 (E1) or a QRSS (T1) PRBS at TTIP and TRING.

0 = disabled

1 = enabled

TLCE

CCR3.3

Transmit Loop-Code Enable. Enables the transmit side to transmit the loop-up code in the transmit

code definition registers (TCD1 and TCD2). See Section 6 for details.

0 = disabled

1 = enabled

LIRST

CCR3.2

Line Interface Reset. Setting this bit from 0 to 1 initiates an internal reset that resets the clock

recovery state machine and recenters the jitter attenuator. Normally this bit is only toggled on

power-up. It must be cleared and set again for a subsequent reset.

IBPV

CCR3.1

Insert Bipolar Violation (BPV). A 0-to-1 transition on this bit causes a single bipolar violation to be

inserted into the transmit data stream. Once this bit has been toggled from 0 to 1, the device waits

for the next occurrence of three consecutive 1s to insert the BPV. This bit must be cleared and set

again for a subsequent error to be inserted (Figure 1-3).

IBE

CCR3.0

Insert Bit Error. A 0-to-1 transition on this bit causes a single logic error to be inserted into the

transmit data stream. This bit must be cleared and set again for a subsequent error to be inserted

(Figure 1-3).

CCR4 (03H): Common Control Register 4

(MSB)

(LSB)

EGL

JAS

JABDS

DJA

TPD

NAME

POSITION

FUNCTION

CCR4.7

Line Build-Out Select Bit 2. Sets the transmitter build-out (Table 7-A for E1, Table 7-B for T1).

CCR4.6

Line Build Out Select Bit 1. Sets the transmitter build-out (Table 7-A for E1, Table 7-B for T1).

CCR4.5

Line Build Out Select Bit 0. Sets the transmitter build-out (Table 7-A for E1, Table 7-B for T1).

EGL

CCR4.4

Receive Equalizer Gain Limit. This bit controls the sensitivity of the receive equalizer (Table 4-I).

JAS

CCR4.3

Jitter Attenuator Path Select

0 = place the jitter attenuator on the receive side

1 = place the jitter attenuator on the transmit side

JABDS

CCR4.2

Jitter Attenuator Buffer Depth Select

0 = 128 bits

1 = 32 bits (use for delay-sensitive applications)

DJA

CCR4.1

Disable Jitter Attenuator

0 = jitter attenuator enabled

1 = jitter attenuator disabled

TPD

CCR4.0

Transmit Power-Down

0 = normal transmitter operation

1 = powers down the transmitter and tri-states the TTIP and TRING pins

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