TLC2872Z, TLC2872Y

Advanced LinCMOS

™ RAIL-TO-RAIL

DUAL OPERATIONAL AMPLIFIERS

SLOS117 – OCTOBER 1992

16

POST OFFICE BOX 655303

APPLICATION INFORMATION

macromodel information

Macromodel information provided was derived using

PSpice

™ Parts™ model generation software. The Boyle

macromodel (see Note 5) and subcircuit in Figure 20 were generated using the TLC2872Z typical electrical and

can be generated to a tolerance of 20% (in most cases):

NOTE 5: G. R. Boyle, B. M. Cohn, D. O. Pederson, and J. E. Solomon, “Macromodeling of Integrated Circuit Operational Amplifiers,”

IEEE Journal

of Solid-State Circuits, SC-9, 353 (1974).

OUT

+

–

+

–

+

–

+

–

+

–

+

–

+

–

+

–

+

–

RD1

60

11

2.653E3

RD2

60

12

2.653E3

R01

8

5

50

R02

7

99

50

RP

3

4

4.310E3

RSS

10

99

925.9E3

VAD

60

4

–.5

VB

9

0

DC 0

VC 3 53 DC .78

VE

54

4

DC .78

VLIM 7

8

DC 0

VLP

91

0

DC 1.9

VLN

0

92

DC 9.4

.MODEL DX D(IS=800.0E–18)

.MODELJXPJF(IS=1.500E–12BETA=1.316E3

+ VTO=–.270)

.ENDS

VCC +

RP

IN –

2

IN+

1

VCC –

VAD

RD1

11

J1

J2

10

RSS

ISS

3

12

RD2

60

VE

54

DE

DP

VC

DC

4

C1

53

R2

6

9

EGND

VB

FB

C2

GCM

GA

VLIM

8

5

RO1

RO2

HLIM

90

DIP

91

DIN

92

VIN

VIP

99

7

.

SUBCKT TLC2872 1 2 3 4 5

C1

11

12

14E–12

C2

6

7

60.00E–12

DC

5

53

DX

DE

54

5

DX

DLP

90

91

DX

DLN

92

90

DX

DP

4

3

DX

EGND 99

0

POLY (2) (3,0) (4,0) 0 .5 .5

FB 7 99

POLY (5) VB VC VE VLP VLN 0

+ 984.9E3 –1E6 1E6 1E6 –1E6

GA

6

0

11 12 377.0E–6

GCM 0 6 10 99 134E–9

ISS

3

10

DC 216.OE–6

HLIM 90

0

VLIM 1K

J1

11

2

10 JX

J2

12

1

10 JX

R2

6

9

100.OE3

Figure 20. Boyle Macromodel and Subcircuit

Macromodels, simulation models, or other models provided by TI,

directly or indirectly, are not warranted by TI as fully representing all

of the specification and operating characteristics of the

semiconductor product to which the model relates.

PSpice and Parts are trademarks of MicroSim Corporation.