TMS320C6472ECTZ datasheet(149/269 Pages) TI1

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TMS320C6472

www.ti.com

SPRS612G

– JUNE 2009 – REVISED JULY 2011

7.8

PLL1 and PLL1 Controller

The C6472 device includes a PLL1 and a software-programmable PLL1 controller. The PLL1 controller is

able to generate different clocks for different parts of the system (i.e., megamodule, DSP core, Peripheral

Data Bus, and other peripherals). There is no hardware CLKMODE selection on the C6472 device. The

PLL multiply factor is set in software after reset.

NOTE

The PLL controller module as described in the TMS320C6472/TMS320TCI648x DSP

Software-Programmable Phase-Locked Loop (PLL) Controller User's Guide (literature

number SPRU806) includes a superset of features, some of which are not supported on the

C6472 DSP. The following sections describe the features that are supported; it should be

assumed that any feature not included in these sections is not supported by the C6472 DSP.

7.8.1

PLL1 Controller Device-Specific Information

7.8.1.1

Internal Clocks and Maximum Operating Frequencies

As shown in Figure 7-14, the PLL1 controller generates several internal clocks including the system clock

output (SYSCLKOUT) and the system clocks (SYSCLK1 through SYSCLK10). SYSCLK10 has a

programmable divider. All other SYSCLKn clocks have a fixed relationship to the CPU clock.

•

SYSCLK1 through SYSCLK6 are used to clock C64x+ Megamodule0 through C64x+ Megamodule5.

•

SYSCLK7 is used for EDMA3CC, EDMA3TC, DMA SCR, Config SCR, boot controller, bridges, and

some peripherals.

•

SYSCLK8 is used for PSC, some peripherals, and SYSCLKOUT external pin.

•

SYSCLK9 is used for shared memory controller and memory.

•

SYSCLK10 is used for C64x+ megamodule trace logic.

NOTE

There is a minimum and maximum operating frequency for CLKIN1 and SYSCLKn. The

clock generator must not be configured to exceed any of these constraints (certain

combinations of external clock input, internal dividers, and PLL multiply ratios might not be

supported). See Table 7-18 for the PLL clocks input and output frequency ranges.

C64x+ Peripheral Information and Electrical Specifications

149

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