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TMS320C6472ECTZ Datasheet(PDF) 153 Page - Texas Instruments |
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TMS320C6472ECTZ Datasheet(HTML) 153 Page - Texas Instruments |
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153 / 269 page  TMS320C6472 www.ti.com SPRS612G – JUNE 2009 – REVISED JULY 2011 7.8.3 PLL1 Controller Registers This section provides a description of the PLL1 controller registers. For details on the operation of the PLL controller module, see the TMS320C6472/TMS320TCI648x DSP Software-Programmable Phase-Locked Loop (PLL) Controller User's Guide (literature number SPRU806). NOTE Not all of the registers documented in the TMS320C6472/TMS320TCI648x DSP Software-Programmable Phase-Locked Loop (PLL) Controller User's Guide (literature number SPRU806) are supported on the C6472. Only those registers documented in this section are supported. Furthermore, only the bits within the registers described here are supported. Users should not write to any reserved memory location or change the value of reserved bits. 7.8.3.1 PLL1 Peripheral ID Register (PID) The peripheral identification register (PID) is a constant register that contains the ID and ID revision number for that module. The PID stores version information used to identify the module. All bits within this register are read-only (writes have no effect). 31 24 23 16 15 8 7 0 Reserved TYPE CLASS REV R-0 R-01 R-08 R-0D LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Figure 7-15. Peripheral ID Register (PID) Table 7-21. Peripheral ID Register (PID) Field Descriptions Bit Field Value Description 31:24 Reserved Reserved 23:16 TYPE 01h Peripheral Type 15:8 CLASS 08h Peripheral Class 7:0 REV 0Dh Peripheral Revision. Identifies the revision level of the specific instance of the peripheral. 7.8.3.2 Reset Type Status Register (RSTYPE) The reset type status register (RSTYPE) is described in Section 7.7.7.1. Copyright © 2009–2011, Texas Instruments Incorporated C64x+ Peripheral Information and Electrical Specifications 153 Submit Documentation Feedback Product Folder Link(s) :TMS320C6472 |
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