TMS320C6472ECTZ datasheet(161/269 Pages) TI1

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TMS320C6472

www.ti.com

SPRS612G

– JUNE 2009 – REVISED JULY 2011

7.9

PLL2 and PLL2 Controller

The C6472 device includes a PLL2 and a software-programmable PLL2 controller. The PLL2 controller

generates different clocks required for Gigabit Ethernet. The PLL multiply factor is set to x20 for PLL2.

NOTE

The PLL controller module as described in the TMS320C6472/TMS320TCI648x DSP

Software-Programmable Phase-Locked Loop (PLL) Controller User's Guide (literature

number SPRU806) includes a superset of features, some of which are not supported on the

C6472 DSP. The following sections describe the features that are supported; it should be

assumed that any feature not included in these sections is not supported by the C6472 DSP.

7.9.1

PLL2 Controller Device-Specific Information

7.9.1.1

Internal Clocks and Maximum Operating Frequencies

As shown in Figure 7-25, the PLL2 controller generates EMAC reference clocks.

•

SYSCLK13 is used by RGMII0 (1000Mbps mode)

•

SYSCLK14 is used by RGMII0 (100Mbps mode) and GMII (1000Mbps mode)

•

SYSCLK15 is used by RGMII0 (10Mbps mode)

•

SYSCLK16 is used by RGMII1 (1000Mbps mode)

•

SYSCLK17 is used by RGMII1 (100Mbps mode)

•

SYSCLK18 is used by RGMII1 (10Mbps mode)

NOTE

There is a fixed operating frequency for CLKIN2 and SYSCLK13-18. The clock generator

must not be configured to exceed any of these constraints (certain combinations of external

clock input, internal dividers, and PLL multiply ratios might not be supported). For the PLL

clocks input and output frequencies, see Table 7-31.

C64x+ Peripheral Information and Electrical Specifications

161

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