TMS320C6472ECTZ datasheet(164/269 Pages) TI1

164 / 269 page

TMS320C6472

SPRS612G

– JUNE 2009 – REVISED JULY 2011

www.ti.com

7.9.3

PLL2 Controller Registers

This section provides a description of the PLL2 controller registers. For details on the operation of the PLL

controller module, see the TMS320C6472/TMS320TCI648x DSP Software-Programmable Phase-Locked

Loop (PLL) Controller User's Guide (literature number SPRU806).

NOTE

Not

all

the

registers

documented

the

TMS320C6472/TMS320TCI648x

DSP

Software-Programmable Phase-Locked Loop (PLL) Controller User's Guide (literature

number SPRU806) are supported on the C6472. Only those registers documented in this

section are supported. Furthermore, only the bits within the registers described here are

supported. You should not write to any reserved memory location or change the value of

reserved bits.

7.9.3.1

PLL2 Peripheral ID Register (PID)

The peripheral identification register (PID) is a constant register that contains the ID and ID revision

number for that module. The PID stores version information used to identify the module. All bits within this

24 23

16 15

Reserved

TYPE

CLASS

REV

R-0

R-01

R-08

R-0D

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Figure 7-26. Peripheral ID Register (PID)

Table 7-34. Peripheral ID Register (PID) Field Descriptions

Bit

Field

Value

Description

31:24

Reserved

23:16

TYPE

01h

Peripheral Type

15:8

CLASS

08h

Peripheral Class

REV

0Dh

Peripheral Revision. Identifies the revision level of the specific instance of the peripheral.

164

C64x+ Peripheral Information and Electrical Specifications

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