TMS320C6472ECTZ datasheet(167/269 Pages) TI1

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TMS320C6472

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SPRS612G

– JUNE 2009 – REVISED JULY 2011

7.9.3.4

PLL2 PLL Controller Command Register (PLLCMD)

The PLL controller command register (PLLCMD) contains the command bit for GO operation. PLLCMD is

shown in Figure 7-29 and described in Table 7-38.

Reserved

R-0

Reserved

Rsvd

GOSET

R-0

R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Figure 7-29. PLL Controller Command Register (PLLCMD)

Table 7-38. PLL Controller Command Register (PLLCMD) Field Descriptions

Bit

Field

Value

Description

31:2

Reserved

Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.

Reserved

Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.

GOSET

GO operation command for SYSCLK rate change and phase alignment. Before setting this bit to 1

to initiate a GO operation, check the GOSTAT bit in the PLLSTAT register to ensure all previous

GO operations have completed.

No effect. Write of 0 clears bit to 0.

Initiates GO operation. Write of 1 initiates GO operation. Once set, GOSET remains set but further

writes of 1 can initiate the GO operation.

C64x+ Peripheral Information and Electrical Specifications

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TMS320C6472ECTZ Datasheet(PDF) 167 Page - Texas Instruments