TMS320C6472ECTZ datasheet(166/269 Pages) TI1

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TMS320C6472

SPRS612G

– JUNE 2009 – REVISED JULY 2011

www.ti.com

7.9.3.3

PLL2 PLL Controller Dividern Register (PLLDIVn)

The PLL controller divider registers 1 through 6 decide the frequency ratio for SYSCLK13 through

SYSCLK18. The PLLDIVn register is shown in Figure 7-28 and described in Table 7-36.

Reserved

R-0

DnEN

Reserved

RATIO

R/W-1

R-0

R/W-x

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Figure 7-28. PLL Controller Divider Register (PLLDIVn)

Table 7-36. PLL Controller Divider Register (PLLDIVn) Field Descriptions

Bit

Field

Value

Description

31:16

Reserved

Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.

DnEN

Divider Dn enable bit.

Divider n is disabled. No clock output.

Divider n is enabled.

14:7

Reserved

Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.

6:0

RATIO

Divider ratio bits.(1)

0-7Fh

÷1 to ÷128. Divide frequency by 1 to divide frequency by 128.

(1)

The divider ratio bits for each divider should be left at the default value.

Table 7-37. PLLDIVn Default Values

PLLDIV1

PLLDIV2

PLLDIV3

PLLDIV4

PLLDIV5

PLLDIV6

SYSCLK13

SYSCLK14

SYSCLK15

SYSCLK16

SYSCLK17

SYSCLK18

MACSEL0[2:0] =

all values except

010

MACSEL0[2:0] =

010

166

C64x+ Peripheral Information and Electrical Specifications

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