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TMS320C6472ECTZ Datasheet(PDF) 173 Page - Texas Instruments |
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TMS320C6472ECTZ Datasheet(HTML) 173 Page - Texas Instruments |
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173 / 269 page ![]() TMS320C6472 www.ti.com SPRS612G – JUNE 2009 – REVISED JULY 2011 expired. The PLL reset time is the amount of wait time needed when resetting the PLL (writing PLLRST = 1), in order for the PLL to properly reset, before bringing the PLL out of reset (writing PLLRST = 0). For the PLL3 reset time value, see Table 7-44. The PLL lock time is the amount of time needed from when the PLL is taken out of reset to when the output clock is ready for use. The PLL3 lock time is given in Table 7-44. Table 7-44. PLL3 Stabilization, Lock, and Reset Times MIN TYP MAX UNIT PLL3 stabilization time 150 μs PLL3 lock time 2000 * C(1) ns PLL3 reset time 128 * C(1) ns (1) C = CLKIN3 cycle time in ns. For example, when CLKIN3 frequency is 25 MHz, use C = 40 ns. 7.10.2 PLL3 Controller Peripheral Register Descriptions The memory map of the PLL3 controller is shown in Table 7-45. Note that only registers documented here are accessible on the C6472. Other addresses in the PLL3 controller memory map should not be modified. Table 7-45. PLL3 Controller Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME 029C 0400 PID Constant Peripheral Identification Register 029C 0404 - 029C 04FC - Reserved 029C 0500 PLLCTL PLL Control Register 029C 0504 - 029C 07FC - Reserved 7.10.3 PLL3 Controller Registers This section provides a description of the PLL3 controller registers. For details on the operation of the PLL controller module, see the TMS320C6472/TMS320TCI648x DSP Software-Programmable Phase-Locked Loop (PLL) Controller User's Guide (literature number SPRU806). NOTE The PLL3 controller registers can only be accessed using the CPU or the emulator. Not all of the registers documented in the TMS320C6472/TMS320TCI648x DSP Software-Programmable Phase-Locked Loop (PLL) Controller User's Guide (literature number SPRU806) are supported on the C6472. Only those registers documented in this section are supported. Furthermore, only the bits within the registers described here are supported. You should not write to any reserved memory location or change the value of reserved bits. Copyright © 2009–2011, Texas Instruments Incorporated C64x+ Peripheral Information and Electrical Specifications 173 Submit Documentation Feedback Product Folder Link(s) :TMS320C6472 |
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