TMS320C6472ECTZ datasheet(190/269 Pages) TI1

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TMS320C6472

SPRS612G

– JUNE 2009 – REVISED JULY 2011

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7.14 TSIP

The TSIP is a multi-link serial interface consisting of a maximum of eight transmit data signals (or links),

eight receive data signals (or links), two frame sync input signals, and two serial clock inputs. The TSIP

module offers support for a maximum of 1024 timeslots for transmit and receive. Typically, 672 timeslots

(DS3) for transmit and receive are utilized on these links. The TSIP module can be configured to use the

frame sync signals and the serial clocks as redundant sources for all transmit and receive data signals or

one frame sync and serial clock for transmit and the second frame sync and clock for receive. The

standard serial data rate for each TSIP transmit and receive data signal is 8.192 Mbps. The standard

frame sync is a one- (or more) bit wide pulse that occurs once every 125

μs or a minimum of one serial

clock period every 1024 serial clocks. At the standard rate and default configuration there are 8 transmit

and 8 receive links that are active. Each serial interface link supports up to 128 8-bit timeslots. This

corresponds to an HMVIP or H.110 serial data rate interface. The serial interface clock frequency may be

either 16.384 MHz (default) or 8.192 MHz. (The clock can be either 1x or 2x the data-bit rate.) Typical

timeslot occupation is 96 timeslots (DS2) for each serial interface link. Seven transmit data links and

seven receive data links are utilized to support the DS3 timeslot requirement. The eighth transmit and

receive links are available to support common channel signaling (CCS). The data rate for the serial

interface links can also be set to 16.384 Mbps or 32.768 Mbps. The maximum number of active serial

links is reduced to four and two, respectively, in these configurations. The serial interface clock frequency

may be either 32.768 MHz or 16.384 MHz for 16.384 Mbps serial links and either 65.536 MHz or

32.768 MHz for 32.768 Mbps serial links.

7.14.1 TSIP0 Peripheral Register Descriptions

Table 7-56. TSIP Module Registers

HEX ADDRESS RANGE

ACRONYM

0250 0000

PID

PID Register

0250 0004

EMUTST

Emulation and Test Register

0250 0008

RST

Reset Register

0250 000C - 0250 007C

Reserved

Table 7-57. Serial Interface Registers

HEX ADDRESS RANGE

ACRONYM

0250 0080

SIUCTL

SIU Global Control Register

0250 0084 - 0250 009C

Reserved

0250 00A0

XCLK

Transmit Clock Source Register

0250 00A4

XCTL

Transmit Control Register

0250 00A8

XSIZE

Transmit Size Register

0250 00AC - 0250 00BC

Reserved

0250 00C0

RCLK

Receive Clock Source Register

0250 00C4

RCTL

Receive Control Register

0250 00C8

RSIZE

Receive Size Register

0250 00CC - 0250 00FC

Reserved

Table 7-58. TDMU Global Registers

HEX ADDRESS RANGE

ACRONYM

0250 0100

TDMUCTL

TDMU Global Control Register

0250 0104

XFRFC

Transmit Free-Running Frame Counter

0250 0108

RFRFC

Receive Free-Running Frame Counter

0250 010C

TDMUCFG

TDMU Global Configuration Register

0250 0110

XBMST

Transmit Channel Bitmap Active Status Register

190

C64x+ Peripheral Information and Electrical Specifications

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