TMS28F008Axy,TMS28F800Axy

1048576 BY 8BIT/524288 BY 16BIT

AUTOSELECT BOOT BLOCK FLASH MEMORIES

SMJS851A − NOVEMBER 1997 − REVISED FEBRUARY 1998

32

POST OFFICE BOX 1443

timing requirements for TMS28F008ASy or ’AEy and TMS28F800ASy or ’AEy (commercial and

extended temperature ranges)

write/erase operations — WE-controlled writes

ALT.

’28F008ASy 70

’28F800ASy 70

’28F008AEy 70

’28F800AEy 70

’28F008ASy80

’28F800ASy80

’28F008AEy80

’28F800AEy80

UNIT

ALT.

SYMBOL

3 V

5 V

3 V

5 V

UNIT

SYMBOL

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

tc( W )

Cycle time, write

tAVAV

100

70

120

80

ns

tc( W )OP

Cycle time, duration of

programming operation

tWHQV1

6

6

6

6

µs

tc( W )ERB

Cycle time, erase

operation (boot block)

tWHQV2

0.3

0.3

0.3

0.3

s

tc( W )ERP

Cycle time, erase

operation (parameter

block)

tWHQV3

0.3

0.3

0.3

0.3

s

tc( W )ERM

Cycle time, erase

operation (main block)

tWHQV4

0.6

0.6

0.6

0.6

s

td(RPR)

Delay time, boot-block

relock

tPHBR

200

100

200

100

ns

th(A)

Hold time, A0 − A18

(see Note 14)

tWHAX

0

0

0

0

ns

th(D)

Hold time, DQ valid

tWHDX

0

0

0

0

ns

th(E)

Hold time, CE

tWHEH

0

0

0

0

ns

th( VPP)

Hold time, VPP from

valid status-register bit

tQVVL

0

0

0

0

ns

th(RP)

Hold time, RP at VHH

from valid status-register

bit

tQVPH

0

0

0

0

ns

th(WP)

Hold time, WP from valid

status-register bit

tWHPL

0

0

0

0

ns

tsu(WP)

Setup time, WP before

write operation

tELPH

90

50

100

50

ns

tsu(A)

Setup time, A0 − A17

(see Note 14)

tAVWH

90

50

100

50

ns

tsu(D)

Setup time, DQ

tDVWH

90

50

100

50

ns

tsu(E)

Setup time, CE before

write operation

tELWL

0

0

0

0

ns

tsu(RP)

Setup time, RP at VHH to

WE going high

tPHHWH

200

100

100

100

ns

tsu( VPP)1

Setup time, VPP to WE

going high

tVPWH

200

100

100

100

ns

tw( W )

Pulse duration, WE low

tWLWH

90

50

100

50

ns

tw( WH)

Pulse duration, WE high

tWLWL

20

10

30

30

ns

trec(RPHW)

Recovery time, RP high

to WE going low

tPHWL

1.5

450

1.5

450

µs

NOTE 14: For 28F800 (8-bit configuration) A−1, A−1 −A18 with A−1 as LSB address. For 28F008 (16-bit configuration): A0−A19 with A0 as LSB

address.