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TMS570LS1114 Datasheet(PDF) 84 Page - Texas Instruments |
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TMS570LS1114 Datasheet(HTML) 84 Page - Texas Instruments |
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84 / 169 page  EMIF_nCS[3:2] 25 Asserted 2 2 EMIF_BA[1:0] EMIF_ADDR[12:0] EMIF_DATA[15:0] EMIF_nWE EMIF_WAIT SETUP Extended Due to EMIF_WAIT 28 Deasserted STROBE STROBE HOLD TMS570LS1114 SPNS188B – OCTOBER 2012 – REVISED FEBRUARY 2015 www.ti.com Figure 6-15. EMIFnWAIT Write Timing Requirements Table 6-27. EMIF Asynchronous Memory Timing Requirements(1) NO. Value Unit MIN NOM MAX Reads and Writes E EMIF clock period 11 ns 2 tw(EM_WAIT) Pulse duration, EMIF_nWAIT 2E ns assertion and deassertion Reads 12 tsu(EMDV-EMOEH) Setup time, EMIF_DATA[15:0] 9 ns valid before EMIFnOE high 13 th(EMOEH-EMDIV) Hold time, EMIF_DATA[15:0] 0 ns valid after EMIF_nOE high 14 tsu(EMOEL-EMWAIT) Setup Time, EMIF_nWAIT 4E+9 ns asserted before end of Strobe Phase(2) Writes 28 tsu(EMWEL-EMWAIT) Setup Time, EMIF_nWAIT 4E+14 ns asserted before end of Strobe Phase(2) (1) E = EMIF_CLK period in ns. (2) Setup before end of STROBE phase (if no extended wait states are inserted) by which EMIFnWAIT must be asserted to add extended wait states. Figure 6-13 and Figure 6-15 describe EMIF transactions that include extended wait states inserted during the STROBE phase. However, cycles inserted as part of this extended wait period should not be counted; the 4E requirement is to the start of where the HOLD phase would begin if there were no extended wait cycles. 84 System Information and Electrical Specifications Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS570LS1114 |
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