TNETV1002IDZHK datasheet(42/102 Pages) TI1

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MCU Subsystem Functional Overview

June 2001 -- Revised December 2002

SPRS180C

4.2.3 MCU SDRAM Memory Interface

The SDRAM memory interface main features are:

•

It operates with the MCU memory interface (MEMINT) so that SDRAM memories can be used on the

same board with Flash and/or SRAM.

•

Supports 16- and 32-bit-wide data bus to SDRAM parts

•

Can address up to 256M bits of SDRAM

•

Operates at the MCU clock speed (47.5 MHz)

•

Flexible programming of SDRAM timing parameters

•

Supports four open SDRAM pages

•

Minimal burst operations supported. (In 16-bit-wide mode, a burst of two is supported.)

The SDRAM interface must be properly initialized before the SDRAM memory can be used. The following

steps are needed for initializing the SDRAM Interface:

•

Program SDRAM_REG for data bus size and the number of dummy cycles used after access to slower

memory device.

•

Program SDRAM parameters in SDRAM_CONFIG, SDRAM_REF_COUNT, and SDRAM_INIT_CONF

•

Write a ‘1’ in the INIT bit of the SDRAM_CNTL register

•

Wait until a ‘1’ is read inside the READY bit of the SDRAM_CNTL register before accessing the SDRAM.

NOTE: By writing a ‘1’ in the INIT bit of the SDRAM_CNTL register, the initialization state

machine of the SDRAM interface module will do the following: Wait for the number of cycles

that is programmed in INIT_NOP_MAX_CNT (should be 100 μs or greater). Send the

specified number of refresh commands that have been programmed into the

INIT_REF_MAX_CNT register.

The SDRAM load-mode-register command is used to configure the SDRAM device mode. Parameters used

in the load-mode-register command are based on the values programmed in the SDRAM interface registers.

TNETV1002IDZHK Datasheet(PDF) 42 Page - Texas Instruments