TNETX3150GGP datasheet(32/113 Pages) TI1

32 / 113 page

TNETX3150/TNETX3150A

ThunderSWITCH™ 15-PORT 10-/100-MBIT/S ETHERNET™ SWITCH

SPWS027F – FEBRUARY 1997 – REVISED SEPTEMBER 1997

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

DRAM and EAM interfaces

All valid frames are passed across the DRAM interface (see Figure 14). The EAM hardware can detect the start

of a new frame from the flag byte information. The first-flag nibble on the DRAM bus (bits 35–32) corresponds

to bits 7–4 of the frame flag (see Figure 12). In conjunction with the DRAM column address strobe, external logic

can access the frame addresses and perform external address lookup, as detailed in the following:

D Use row-address strobe (DRAS) and column-address strobe (DCAS) to identify the position of the forward

pointer, the top nibble of the flag byte, and whether the nibble contains the start of frame code 01XX.

Bit 35 of the forward pointer should be zero to denote a start of frame. If it is high, the frame is an IOB link

buffer and not the start-of-data frame (bits 34, 33, and 32 contain parity information for the three forward

point or data bytes).

D Bits 31–28 of the forward pointer contain the pre-tag nibble applied to the uplink (when used in uplink mode).

See description of Port 00 uplink port.

D Bits 27–24 denote the active port number (port 00 = 0000, port 01 = 0001, etc.).

D Use the DRAM column-address strobe (DCAS) to identify the presence of destination and source address

data on the DRAM interface.

D Perform address processing.

D Present the destination-channel bit map not more than 12 memory cycles after the high nibble of the start

flag is transmitted on the DRAM interface.

D External address timing is shown in Figure 41.

TNETX3150GGP Datasheet(PDF) 32 Page - Texas Instruments