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TMS320C54CST Datasheet(PDF) 46 Page - Texas Instruments |
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TMS320C54CST Datasheet(HTML) 46 Page - Texas Instruments |
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46 / 171 page  Functional Overview 46 November 2001 − Revised September 2003 SPRS187B 3.12.1 Features The DMA has the following features: • The DMA operates independently of the CPU. • The DMA has six channels. The DMA can keep track of the contexts of six independent block transfers. • The DMA has higher priority than the CPU for both internal and external accesses. • Each channel has independently programmable priorities. • Each channel’s source and destination address registers can have configurable indexes through memory on each read and write transfer, respectively. The address may remain constant, be post-incremented, be post-decremented, or be adjusted by a programmable value. • Each read or write internal transfer may be initialized by selected events. • On completion of a half- or entire-block transfer, each DMA channel may send an interrupt to the CPU. • The DMA can perform double-word internal transfers (a 32-bit transfer of two 16-bit words). 3.12.2 DMA External Access The 54CST DMA supports external accesses to extended program memory. A maximum of two DMA channels can be used for external memory accesses. The DMA external accesses require a minimum of 8 cycles for external writes and a minimum of 11 cycles for external reads assuming the XIO02 is in consecutive mode (CONSEC = 1), wait state is set to two, and CLKOUT is not divided (DIVFCT = 00). The control of the bus is arbitrated between the CPU and the DMA. While the DMA or CPU is in control of the external bus, the other will be held-off via wait states until the current transfer is complete. The DMA takes precedence over XIO requests. • Only two channels are available for external accesses. (One for external reads and one for external writes.) • Single-word (16-bit) transfers are supported for external accesses. • The DMA does not support transfers from the peripherals to external memory. • The DMA does not support transfers from external memory to the peripherals. • The DMA does not support external-to-external transfers. 15 14 13 12 11 10 8 AUTOINIT DINM IMOD CTMOD SLAXS SIND 7654 210 DMS DLAXS DIND DMD Figure 3−16. DMA Transfer Mode Control Register (DMMCRn) These new bit fields were created to allow the user to define the space-select for the DMA (internal/external). Also, a new extended destination data page (XDSTDP[6:0], subaddress 029h) and extended source data page (XSRCDP[6:0], subaddress 028h) have been created. The functions of the DLAXS and SLAXS bits are as follows: DLAXS(DMMCRn[5]) Destination 0 = No external access (default internal) 1 = External access SLAXS(DMMCRn[11]) Source 0 = No external access (default internal) 1 = External access |
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