CY2071A
Document #: 38-07139 Rev. *A
Page 5 of 8
Switching Characteristics, Commercial 3.3V[8]
Parameter
Name
Description
Min.
Typ.
Max.
Unit
t1
Output Period
Clock output range
3.3V operation
15-pF load
CY2071AS
10
[100 MHz]
2000
[500 kHz]
ns
CY2071AF
12.50
[80 MHz]
2000
[500 kHz]
ns
t1A
Clock Jitter
Peak-to-peak period jitter (t1 max. – t1 min.),
% of clock period, fOUT ≤ 16 MHz
0.8
1
%
t1B
Clock Jitter
Peak-to-peak period jitter
(16 MHz
≤ f
OUT ≤ 50 MHz)
350
500
ps
t1C
Clock Jitter[9]
Peak-to-peak period jitter (fOUT > 50 MHz)
250
350
ps
Output Duty Cycle
Duty cycle[10, 11] for outputs, (t2 ÷ t1)
fOUT ≤ 60 MHz
45%
50%
55%
Output Duty Cycle[9] Duty cycle[11] for outputs, (t2 ÷ t1),
fOUT > 60 MHz
40%
50%
60%
t3
Rise Time[9]
Output clock rise time
1.5
2.5
ns
t4
Fall Time[9]
Output clock fall time
1.5
2.5
ns
t5
Skew
Skew delay between any two outputs with
identical frequencies (generated by the PLL)
0.5
ns
Switching Characteristics, Industrial 5.0V[8]
Parameter
Name
Description
Min.
Typ.
Max.
Unit
t1
Output Period
Clock output range
5.0V operation
25-pF load
CY2071AI
10
[100 MHz]
2000
[500 kHz]
ns
CY2071AFI
11.1
[90 MHz]
2000
[500 kHz]
ns
t1A
Clock Jitter
Peak-to-peak period jitter (t1 max. – t1 min.),
% of clock period, fOUT ≤ 16 MHz
0.8
1
%
t1B
Clock Jitter
Peak-to-peak period jitter
(16 MHz
≤ f
OUT ≤ 50 MHz)
350
500
ps
t1C
Clock Jitter[9]
Peak-to-peak period jitter (fOUT > 50 MHz)
250
350
ps
Output Duty Cycle
Duty cycle[10, 11] for outputs, (t2 ÷ t1)
fOUT ≤ 60 MHz
45%
50%
55%
Output Duty Cycle[9] Duty cycle[11] for outputs, (t2 ÷ t1),
fOUT > 60 MHz
40%
50%
60%
t3
Rise time[9]
Output clock rise time
1.5
2.5
ns
t4
Fall time[9]
Output clock fall time
1.5
2.5
ns
t5
Skew
Skew delay between any two outputs with
identical frequencies (generated by the PLL)
0.5
ns
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