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SN0402002DBVR Datasheet(PDF) 3 Page - Texas Instruments |
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SN0402002DBVR Datasheet(HTML) 3 Page - Texas Instruments |
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3 / 31 page  RESET GND MR V DD SENSE WDI 3 2 4 6 1 5 RSTVDD GND MR V DD SENSE RSTSENSE 3 2 4 6 1 5 RESET GND MR V DD PFI PFO 3 2 4 6 1 5 TPS3103, TPS3106, TPS3110 www.ti.com SLVS363F – AUGUST 2001 – REVISED NOVEMBER 2015 5 Available Options DEVICE RESET OUTPUT RSTSENSE, RSTVDD OUTPUT SENSE INPUT WDI INPUT PFO OUTPUT TPS3103 Open-drain Open-drain TPS3106 Open-drain ✓ TPS3110 Push-pull ✓ ✓ 6 Pin Configuration and Functions TPS3103 DBV Package TPS3106 DBV Package 6-Pin SOT-23 6-Pin SOT-23 Top View Top View TPS3110 DBV Package 6-Pin SOT-23 Top View Pin Functions PIN I/O DESCRIPTION NAME TPS3103 TPS3106 TPS3110 GND 2 2 2 — GND Manual-reset input. Pull low to force a reset. RESET remains low as long as MR 3 3 3 I MR is low and for the time-out period after MR goes high. Leave unconnected or connect to VDD when unused. Power-fail input compares to 0.551 V with no additional delay. Connect to PFI 4 — — I VDD if not used. PFO 5 — — O Power-fail output. Goes high when voltage at PFI rises above 0.551 V. RESET 1 — 1 O Active-low reset output. Either push-pull or open-drain output stage. Active-low reset output. Logic level at RSTSENSE only depends on the RSTSENSE — 5 — O voltage at SENSE and the status of MR. Active-low reset output. Logic level at RSTVDD only depends on the voltage RSTVDD — 1 — O at VDD and the status of MR. A reset is asserted if the voltage at SENSE is lower than 0.551 V. Connect SENSE — 4 4 I to VDD if unused. VDD 6 6 6 I Supply voltage. Powers the device and monitors its own voltage. Watchdog timer input. If WDI remains high or low longer than the time-out WDI — — 5 I period, then reset is triggered. The timer clears when reset is asserted or when WDI sees a rising edge or a falling edge. Copyright © 2001–2015, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: TPS3103 TPS3106 TPS3110 |
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