Switching Frequency

100 k

R

500 [kHz]

=

x

TPS54972

www.ti.com

SLVS437B – AUGUST 2002 – REVISED AUGUST 2010

DETAILED DESCRIPTION

UNDERVOLTAGE LOCKOUT (UVLO)

The TPS54972 incorporates an undervoltage lockout circuit to keep the device disabled when the input voltage

(VIN) is insufficient. During power up, internal circuits are held inactive until VIN exceeds the nominal UVLO

threshold voltage of 2.95 V. Once the UVLO start threshold is reached, device start-up begins. The device

operates until VIN falls below the nominal UVLO stop threshold of 2.80 V. Hysteresis in the UVLO comparator,

and a 2.5-µs rising and falling edge deglitch circuit reduce the likelihood of shutting the device down due to noise

on VIN.

ENABLE (ENA)

The enable pin, ENA, provides a digital control to enable or disable (shut down) the TPS54972. An input voltage

of 1.4 V or greater ensures the TPS54972 is enabled. An input of 0.9 V or less ensures the device operation is

disabled. These are not standard logic thresholds, even though they are compatible with TTL outputs.

When ENA is low, the oscillator, slow-start, PWM control and MOSFET drivers are disabled and held in an initial

state ready for device start-up. On an ENA transition from low to high, device start-up begins with the output

starting from 0 V.

SLOW-START

The slow-start circuit provides start-up slope control of the output voltage to limit in-rush currents. The nominal

internal slow-start rate is 0.25 V/ms with the minimum rate being 0.35 V/ms. When the voltage on REFIN rises

faster than the internal slope or is present when device operation is enabled, the output rises at the internal rate.

If the reference voltage on REFIN rises more slowly, then the output rises at approximately the same rate as

REFIN.

VBIAS REGULATOR (VBIAS)

The VBIAS regulator provides internal analog and digital blocks with a stable supply voltage over variations in

junction temperature and input voltage. A high quality, low-ESR, ceramic bypass capacitor is required on the

VBIAS pin. X7R or X5R grade dielectrics are recommended because their values are more stable over

temperature. The bypass capacitor should be placed close to the VBIAS pin and returned to AGND. External

loading on VBIAS is allowed, with the caution that internal circuits require a minimum VBIAS of 2.70 V, and

external loads on VBIAS with ac or digital switching noise may degrade performance. The VBIAS pin may be

useful as a reference voltage for external circuits.

VOLTAGE REFERENCE

The input range for this external reference is 0.2 V to 1.75 V. Above this level, the internal bandgap reference

overrides the externally supplied reference voltage.

OSCILLATOR AND PWM RAMP

The oscillator frequency can be set to an internally fixed value of 350 kHz by leaving the RT pin unconnected

(floating). If a different frequency of operation is required for the application, the oscillator frequency can be

externally adjusted from 280 to 700 kHz by connecting a resistor to the RT pin to ground. The switching

frequency is approximated by the following equation, where R is the resistance from RT to AGND:

The following table summarizes the frequency selection configurations:

SWITCHING FREQUENCY

RT PIN

350 kHz, internally set

Float

Externally set 280 kHz to 700 kHz

R = 68 k

Ω to 180 kΩ

Copyright © 2002–2010, Texas Instruments Incorporated

Submit Documentation Feedback

13