VITESSE

SEMICONDUCTOR CORPORATION

Advance Product Information

VSC8162

2.488 Gbit/sec SONET/SDH

1:16 Demux with Clock Recovery

Page 2

© VITESSE SEMICONDUCTOR CORPORATION

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

9/14/98

G52209-0, Rev. 2.0

Functional Description

Clock Recovery:

The clock recovery unit (CRU) consists of a phase detector, voltage controlled oscillator (VCO), loop filter

and frequency control unit (FCU). The components of the CRU are fully integrated on the VSC8162. A

19.44MHz reference clock (REFCLK) is required for proper operation of the Clock Recovery Unit (CRU). Jit-

ter tolerance of the CRU is well above the SONET and SDH jitter tolerance masks. In addition, the recovered

high speed clock is output on the CLKO pins.

Incoming data is presented to both the clock recovery circuit and the data retiming circuit. When the CRU is

in lock mode, a phase detector circuit is effective. When there is a phase error between the incoming data and

the on-chip VCO, the phase detector output raises or lowers the voltage on the loop filter to null the phase dif-

ference.

The frequency control unit (FCU) monitors the frequency difference between the reference clock, REFCK,

differ by less than 1 MHz, the FCU only passively monitors the frequency difference continuously without

sending any corrections to the loop filter. In the event of the loss of an input signal, or if the input is switching

lock detector will assert the LOL output. LOL is designed to be asserted from between 2.3us and 100us after the

interruption of data.

When NRZ data is again presented at the data input, the phase detector will permit the VCO to lock to the

incoming data. Hysteresis is provided which delays the deassertion of LOL until approximately 160us follow-

ing the restoration of valid data.

The NOREF output will go high to indicate that there is no signal on the REFCK input, or that the REFCK

is more than approximately 25% above or below the expected value.

Retiming:

The retiming decision circuit functions as a D Flip Flop. The recovered clock nominally clocks the decision

circuit in the center of the data eye. Internally, the recovered clock is duplicated to create 32 copies, with a phase

difference between each of 1/32 of a unit interval. The PADJ[4:0] inputs select which of the 32 phases are to be

used to retime the data. Certain lightwave systems employing optical amplifiers suffer from noise in the leading

edge of the data eye. Therefore these systems may achieve their lowest Bit Error Rate (BER) by delaying the

retiming point until later in the eye. The PADJ inputs can be strapped to generate a fixed delay or the customer

can develop a dynamic circuit which can select the optimum retiming point during a training sequence. The

retimed high speed data can be monitored using the RTDO pins.

Figure 1 and Table 1 indicate how the PADJ pins adjust the sampling point in the data eye. The step size of

each unit interval is approximately 12.5ps. The values in Table 1 are not exact and should be used only as an

approximation of the expected delay. Due to environmental variations, the actual measured value at any point

could vary by as much as +/- 1 step size. It should be noted that PADJ[4:0] = ‘00000’ always corresponds to the

sampling center point and that the delay between unit intervals increases monotonically.