PRELIMINARY
CY23S08
Document #: 38-07265 Rev. *D
Page 4 of 8
t3
Rise Time[7] (–1H, -2H)
Measured between 0.8V and 2.0V, 30-pF load
1.50
ns
t4
Fall Time[7] (–1, –2, –3, –4) Measured between 0.8V and 2.0V, 30-pF load
2.20
ns
t4
Fall Time[7] (–1, –2, –3, –4) Measured between 0.8V and 2.0V, 15-pF load
1.50
ns
t4
Fall Time[7] (–1H, 2H)
Measured between 0.8V and 2.0V, 30-pF load
1.25
ns
t5
Output to Output Skew on
same Bank (–1)[7]
All outputs equally loaded
200
ps
Output to Output Skew on
same Bank
(–1H,–2,–2H,–3)[7]
All outputs equally loaded
150
ps
Output to Output Skew on
same Bank (–4)[7]
All outputs equally loaded
100
ps
Output to Output Skew
(–1H, -2H)
All outputs equally loaded
200
ps
Output Bank A to Output
Bank B Skew (–1,–2, –3)
All outputs equally loaded
300
ps
Output Bank A to Output
Bank B Skew (–4)
All outputs equally loaded
215
ps
Output Bank A to Output
Bank B Skew (–1H)
All outputs equally loaded
250
ps
t6
Delay, REF Rising Edge to
FBK Rising Edge[7]
Measured at VDD/2
–250
0
+275
ps
t7
Device to Device Skew[7]
Measured at VDD/2 on the FBK pins of devic-
es
0700
ps
t8
Output Slew Rate[7]
Measured between 0.8V and 2.0V on –1H,
–2H device using Test Circuit #2
1V/ns
tJ
Cycle to Cycle Jitter[7]
(–1, –1H)
Measured at 66.67 MHz, loaded outputs, 15,
30-pF loads: 133 MHz, 15-pF load
125
ps
Cycle to Cycle Jitter[7]
(–2)
Measured at 66.67 MHz, loaded outputs,
15-pF load
300
ps
Cycle to Cycle Jitter[7]
(–2)
Measured at 66.67 MHz, loaded outputs,
30-pF load
400
ps
tJ
Cycle to Cycle Jitter[7]
(–3,–4)
Measured at 66.67 MHz, loaded outputs
15,30-pF loads
200
ps
tLOCK
PLL Lock Time[7]
Stable power supply, valid clocks presented
on REF and FBK pins
1.0
ms
Switching Characteristics for CY23S08SC-XX Commercial Temperature Devices (continued)[8]
Parameter
Name
Test Conditions
Min.
Typ.
Max.
Unit
Switching Waveforms
Duty Cycle Timing
t1
t2
1.4V
1.4V
1.4V
All Outputs Rise/Fall Time
OUTPUT
t3
3.3V
0V
0.8V
2.0V
2.0V
0.8V
t4
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