FDC37N769 datasheet(13/138 Pages) SMSC

13 / 138 page

SMSC DS – FDC37N769

Page 13 of 137

Rev. 12/21/2000

TQFP

PIN #

NAME

SYMBOL

BUFFER

TYPE

DESCRIPTION

ALTERNATE IR PINS/MISC

14.318

MHz Input

Clock

CLK14

ICLK

The external connection to a single source 14.318

MHz clock.

IR Receive

IRRX2

IR Receive input

IR Transmit

(Note

IRTX2

O12PD

IR transmit output

Drive 2/

Address X/

Interrupt

Request B

DRV2

nADRX

IRQ_B

I/OD12/

(O12/

OD12)

In PS/2 mode, this input indicates whether a second

drive is connected; DRV2 should be low if a second

drive is connected. This status is reflected in a read

of Status Register A.

Active low address decode out: used to decode a 1,

8, or 16 byte address block. (An external pull-up is

required). Refer to Configuration registers CR03,

CR08 and CR09 for more information.

The interrupt request from a logical device or IRQIN

may be output on IRQ_B. Refer to the configuration

registers for more information. If EPP or ECP Mode

is enabled, this output is pulsed low and released to

allow sharing of interrupts.

IR Mode/ IR

Receive 3

IRMODE

IRR3

O6/IS

IR mode

IR Receive 3

Power

Good/

nGame

Port Chip

Select

PWRGD

nGAMECS

I/O4

This active high input indicates that the power (VCC)

is valid.

For device operation PWRGD must be

active.

When PWRGD is inactive, all inputs are

disconnected and put into a low power mode; all

outputs are put into high impedance. The contents af

all registers are preserved as long as VCC is valid.

The output driver current drain when PWRGD is

inactive mode drops to ISTBY - standby current.

This is the Game Port Chip Select output - active low.

It will go active when the I/O address, qualified by

AEN, matches that selected in Configuration register

CR1E.

External

Interrupt

Input

IRQIN

This pin is used to steer an interrupt signal from an

external device onto one of eight IRQ outputs IRQA-

POWER INTERFACE

13,70

Power

VCC

Positive Supply Voltage.

4,45,

65,93

Ground

GND

Ground Supply.

Note 1:nRI and the UART interrupts are active when PWRGD is active and the UARTS are either fully powered or in

AUTOPOWER DOWN mode.

Note 2:The FDD output pins multiplexed in the PARALLEL PORT INTERFACE are OD drivers only and are not affected

by the FDD Output Driver Controls (see section CR05 on page 102).

Note 3:Active (push-pull) output drivers are required on these pins in the enhanced parallel port

modes.

Note 4:An external pull-up must be provided for IOCHRDY.

Note 5:The pull-down on this pin is always active including when the output driver is tristated and regardless of the state

of PWRGD.

Buffer Type Summmary

Table 2 below describes the buffer types shown in Table 1. All values are specified at Vcc = +3.3v, ±10%

Table 2 - FDC37N769 3.3V Buffer Type Summary

FDC37N769 Datasheet(PDF) 13 Page - SMSC Corporation

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