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NCP4208

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control input voltage to the positive input is set via the VID

logic according to the voltages listed in Table 8. The VID

code is set using the VID Input pins or it can be programmed

over the I2C using the VOUT_Command. By default, the

NCP4208 outputs a voltage corresponding to the VID

Inputs. To output a voltage following the VOUT_Command

the user first needs to program the required VID Code. Then

the VID_EN Bits need to be enabled. The following is the

sequence:

1. Program the required VID Code to the

VOUT_Command code (0x21).

2. Set the VID_EN bit (Bit 3) in the VR Config 1A

(0xD2) and on the VR Config 1B (0xD3).

This voltage is also offset by the droop voltage for active

positioning of the output voltage as a function of current,

commonly known as active voltage positioning. The output

of the amplifier is the COMP pin, which sets the termination

voltage for the internal PWM ramps.

The negative input (FB) is tied to the output sense location

with Resistor RB and is used for sensing and controlling the

output voltage at this point. A current source (equal to IREF)

from the FB pin flowing through RB is used for setting the

no load offset voltage from the VID voltage. The no load

voltage is negative with respect to the VID DAC for Intel

CPU’s. The main loop compensation is incorporated into the

feedback network between FB and COMP.

An offset voltage can be added to the control voltage over

the serial interface. This is done using Bits <5:0> of the

VOUT_CAL (0xDD) Command. The max offset that can be

applied is

±200 mV. The LSB size id 6.25 mV. A positive

offset is applied when Bit 5 = 0. A negative offset is applied

when Bit 5 = 1.

Table 4. Offset Codes

VOUT_Cal CODE

OFFSET VOLTAGE

0 0001

+6.25 mV

0 0010

+12.5 mV

0 0011

+18.75 mV

Dynamic VID

The NCP4208 has the ability to dynamically change the

VID inputs while the controller is running. This allows the

output voltage to change while the supply is running and

supplying current to the load. This is commonly referred to

as Dynamic VID (DVID). A DVID can occur under either

light or heavy load conditions. The processor signals the

controller by changing the VID inputs (or by programming

a new VOUT_Command) in a single or multiple steps from

the start code to the finish code. This change can be positive

or negative.

When a VID bit changes state, the NCP4208 detects the

change and ignores the DAC inputs for a minimum of 200 ns.

This time prevents a false code due to logic skew while the

VID inputs are changing. Additionally, the first VID change

initiates the PWRGD and CROWBAR blanking functions for

a minimum of 100

ms to prevent a false PWRGD or

CROWBAR event. Each VID change resets the internal

timer.

If a VID off code is detected the NCP4208 will wait for

msec to ensure that the code is correct before initiating a

shutdown of the controller.

The NCP4208 also uses the TON_Transition (0xD6) to

limit the DVID slew rates. These can be encountered when

the system does a large single VID step for power state

changes, thus the DVID slew rate needs to be limited to

prevent large inrush currents.

The transition slew rate is programmed using Bits <2:0>

of the Ton_Transition (0xD6) command code. Table 5

provides the transition rate values.

Table 5. Transition Rate Codes

Code

Transition Rate (V/msec)

000

001

010

5 = default

011

100

101

110

111

Enhanced transient Mode

The NCP4208 incorporates enhanced transient response

for both load step up and load release. For load step up it

senses the output of the error amp to determine if a load step

up has occurred and then sequences on the appropriate

number of phases to ramp up the output current.

For load release, it also senses the output of the error amp

and uses the load release information to trigger the TRDET

pin, which is then used to adjust the error amp feedback for

optimal positioning. This is especially important during

high frequency load steps.

Additional information is used during load transients to

ensure proper sequencing and balancing of phases during

high frequency load steps as well as minimizing the stress on

components such as the input filter and MOSFET’s.

Current Reference

The IREF pin is used to set an internal current reference.

This reference current sets IFB. A resistor to ground

programs the current based on the 1.8 V output.

IREF +

1.8 V

RIREF

(eq. 8)

Typically, RIREF is set to 121 kW to program IREF = 15 mA.

Internal Delay Timer

The delay times for the startup timing sequence are set by

an internal timer. The default time is 2 msec which can be

changed through the I2C interface. This timer is used for

multiple delay timings (TD1, TD3, and TD5) during the

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