ST72561 datasheet(175/262 Pages) STMICROELECTRONICS

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ST72561

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beCAN CONTROLLER (Cont’d)

10.9.3.3 Low Power Mode (Sleep)

To reduce power consumption, beCAN has a low

power mode called Sleep mode. This mode is en-

tered on software request by setting the SLEEP bit

in the CMCR register. In this mode, the beCAN

clock is stopped. Consequently, software can still

access the beCAN registers and mailboxes but the

beCAN will not update the status bits.

Example: If software requests entry to initializa-

tion mode by setting the INRQ bit while beCAN is

in sleep mode, it will not be acknowledged by the

hardware, INAK stays cleared.

beCAN can be woken up (exit Sleep mode) either

by software clearing the SLEEP bit or on detection

of CAN bus activity.

On CAN bus activity detection, hardware automat-

ically performs the wake-up sequence by clearing

the SLEEP bit if the AWUM bit in the CMCR regis-

ter is set. If the AWUM bit is cleared, software has

to clear the SLEEP bit when a wake-up interrupt

occurs, in order to exit from sleep mode.

Note: If the wake-up interrupt is enabled (WKUIE

bit set in CIER register) a wake-up interrupt will be

generated on detection of CAN bus activity, even if

the beCAN automatically performs the wake-up

sequence.

After the SLEEP bit has been cleared, Sleep mode

is exited once beCAN has synchronized with the

CAN bus, refer to Figure 96.beCAN Operating

Modes. The sleep mode is exited once the SLAK

bit has been cleared by hardware.

10.9.3.4 Test Mode

Test mode can be selected by the SILM and LBKM

bits in the CDGR register. These bits must be con-

figured while beCAN is in Initialization mode. Once

test mode has been selected, beCAN is started in

Normal mode.

10.9.3.5 Silent Mode

The beCAN can be put in Silent mode by setting

the SILM bit in the CDGR register.

In Silent mode, the beCAN is able to receive valid

data frames and valid remote frames, but it sends

only recessive bits on the CAN bus and it cannot

start a transmission. If the beCAN has to send a

dominant bit (ACK bit, overload flag, active error

flag), the bit is rerouted internally so that the CAN

Core monitors this dominant bit, although the CAN

bus may remain in recessive state. Silent mode

can be used to analyze the traffic on a CAN bus

without affecting it by the transmission of dominant

bits (Acknowledge Bits, Error Frames).

Figure 97. beCAN in Silent Mode

10.9.3.6 Loop Back Mode

The beCAN can be set in Loop Back Mode by set-

ting the LBKM bit in the CDGR register. In Loop

Back Mode, the beCAN treats its own transmitted

messages as received messages and stores them

(if they pass acceptance filtering) in the FIFO.

Figure 98. beCAN in Loop Back Mode

This mode is provided for self-test functions. To be

independent of external events, the CAN Core ig-

nores acknowledge errors (no dominant bit sam-

pled in the acknowledge slot of a data / remote

frame) in Loop Back Mode. In this mode, the be-

CAN performs an internal feedback from its Tx

output to its Rx input. The actual value of the CAN-

RX input pin is disregarded by the beCAN. The

transmitted messages can be monitored on the

CANTX pin.

beCAN

CANTX CANRX

beCAN

CANTX CANRX

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