ST72561 datasheet(241/262 Pages) STMICROELECTRONICS

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ST72561

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12.10 CONTROL PIN CHARACTERISTICS

12.10.1 Asynchronous RESET Pin

Subject to general operating conditions for VDD, fOSC, and TA unless otherwise specified.

Figure 138. Typical Application with RESET pin 7)8)9)

Notes:

1. Data based on characterization results, not tested in production.

2. Hysteresis voltage between Schmitt trigger switching levels.

3. Not tested in production. The IIO current sunk must always respect the absolute maximum rating specified in Section

12.2.2 and the sum of IIO (I/O ports and control pins) must not exceed IVSS.

4. The RON pull-up equivalent resistor is based on a resistive transistor.

5. To guarantee the reset of the device, a minimum pulse has to be applied to the RESET pin. All short pulses applied on

RESET pin with a duration below th(RSTL)in can be ignored.

6. The reset network (the resistor and two capacitors) protects the device against parasitic resets, especially in a noisy

environments.

7. The output of the external reset circuit must have an open-drain output to drive the ST7 reset pad. Otherwise the device

can be damaged when the ST7 generates an internal reset (watchdog).

8. Whatever the reset source is (internal or external), the user must ensure that the level on the RESET pin can go below

the VIL max. level specified in Section 12.10.1 . Otherwise the reset will not be taken into account internally.

9. Because the reset circuit is designed to allow the internal RESET to be output in the RESET pin, the user must ensure

that the current sunk on the RESET pin (by an external pull-p for example) is less than the absolute maximum value spec-

ified for IINJ(RESET) in Section 12.2.2 on page 222.

Symbol

Parameter

Conditions

Min

Typ 1)

Max

Unit

VIL

Input low level voltage 1)

0.3xVDD

VIH

Input high level voltage 1)

0.7xVDD

Vhys

Schmitt trigger voltage hysteresis 2)

VDD=5V

1.5

VOL

Output low level voltage 3)

VDD=5V

IIO=+5mA

0.68

0.95

IIO=+2mA

0.28

0.45

RON

Weak pull-up equivalent resistor 4)

VIN=VSS

Ω

tw(RSTL)out Generated reset pulse duration

Internal reset source

µs

th(RSTL)in External reset pulse hold time

2.5

µs

tg(RSTL)in Filtered glitch duration

200

0.01

µF

VDD

0.01

µF

EXTERNAL

RESET

CIRCUIT 6)

USER

VDD

4.7k

Ω

Required if LVD is disabled

Recommended

if LVD is disabled

ST72XXX

PULSE

GENERATOR

Filter

RON

VDD

WATCHDOG

LVD RESET

INTERNAL

RESET

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