ST72561 datasheet(259/262 Pages) STMICROELECTRONICS

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ST72561

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15 IMPORTANT NOTES

15.1

CLEARING

ACTIVE

INTERRUPTS

OUTSIDE INTERRUPT ROUTINE

When an active interrupt request occurs at the

same time as the related flag or interrupt mask is

being cleared, the CC register may be corrupted.

Concurrent interrupt context

The symptom does not occur when the interrupts

are handled normally, i.e. when:

– The interrupt request is cleared (flag reset or in-

terrupt mask) within its own interrupt routine

– The interrupt request is cleared (flag reset or in-

terrupt mask) within any interrupt routine

– The interrupt request is cleared (flag reset or in-

terrupt mask) in any part of the code while this in-

terrupt is disabled

If these conditions are not met, the symptom can

be avoided by implementing the following se-

quence:

Perform SIM and RIM operation before and after

resetting an active interrupt request

Ex:

SIM

reset flag or interrupt mask

RIM

Nested interrupt context

The symptom does not occur when the interrupts

are handled normally, i.e. when:

– The interrupt request is cleared (flag reset or in-

terrupt mask) within its own interrupt routine

– The interrupt request is cleared (flag reset or in-

terrupt mask) within any interrupt routine with

higher or identical priority level

– The interrupt request is cleared (flag reset or in-

terrupt mask) in any part of the code while this in-

terrupt is disabled

If these conditions are not met, the symptom can

be avoided by implementing the following se-

quence:

PUSH CC

SIM

reset flag or interrupt mask

POP CC

15.2 CAN FIFO CORRUPTION

The beCAN FIFO gets corrupted when a message

is received and simultaneously a message is re-

leased while FMP=2. For details and a description

of the workaround refer to Section 10.9.7.1 on

page 189.

15.3 FLASH/FASTROM DEVICES ONLY

15.3.1 LINSCI wrong break duration

SCI Mode

A single break character is sent by setting and re-

setting the SBK bit in the SCICR2 register. In

some cases, the break character may have a long-

er duration than expected:

- 20 bits instead of 10 bits if M=0

- 22 bits instead of 11 bits if M=1.

In the same way, as long as the SBK bit is set,

break characters are sent to the TDO pin. This

may lead to generate one break more than expect-

ed.

Occurrence

The occurrence of the problem is random and pro-

portional to the baudrate. With a transmit frequen-

19200

baud

(fCPU=8MHz

and

SCI-

BRR=0xC9), the wrong break duration occurrence

is around 1%.

Workaround

If this wrong duration is not compliant with the

communication protocol in the application, soft-

ware can request that an Idle line be generated

before the break character. In this case, the break

duration is always correct assuming the applica-

tion is not doing anything between the idle and the

break. This can be ensured by temporarily disa-

bling interrupts.

The exact sequence is:

- Disable interrupts

- Reset and Set TE (IDLE request)

- Set and Reset SBK (Break Request)

- Re-enable interrupts

LIN mode

If the LINE bit in the SCICR3 is set and the M bit in

the SCICR1 register is reset, the LINSCI is in LIN

master mode. A single break character is sent by

setting and resetting the SBK bit in the SCICR2

have a longer duration than expected:

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