TC55VCM208ASTN40 datasheet(9/12 Pages) TOSHIBA

9 / 12 page

TC55VCM208ASTN40,55

2003-08-11

9/12

Note:

(1)

R/W remains HIGH for the read cycle.

(2)

If CE1 goes LOW(or CE2 goes HIGH) coincident with or after R/W goes LOW, the outputs will remain

at high impedance.

(3)

If CE1 goes HIGH(or CE2 goes LOW) coincident with or before R/W goes HIGH, the outputs will

remain at high impedance.

(4)

If OE is HIGH during the write cycle, the outputs will remain at high impedance.

(5)

Because I/O signals may be in the output state at this time, input signals of reverse polarity must not be

applied.

DATA RETENTION CHARACTERISTICS (Ta

= −40° to 85°C)

SYMBOL

PARAMETER

MIN

TYP

MAX

UNIT

VDH

Data Retention Supply Voltage

1.5



3.6

VDH = 3.6 V Ta = −40~85°C



= −40~40°C



IDDS2

Standby Current

VDH = 3.0 V

= −40~85°C



µA

tCDR

Chip Deselect to Data Retention Mode Time



Recovery Time



CONTROLLED DATA RETENTION MODE

(See Note 1)

CE2 CONTROLLED DATA RETENTION MODE

(See Note 3)

VDD

2.3 V

GND

VIL

DATA RETENTION MODE

tCDR

VDD

0.2 V

VIH

CE2

CE1

VDD

2.3 V

GND

VIH

DATA RETENTION MODE

(See Note 2)

tCDR

VDD

VDD − 0.2 V

TC55VCM208ASTN40 Datasheet(PDF) 9 Page - Toshiba Semiconductor

TC55VCM208ASTN40 Datasheet(HTML) 9 Page - Toshiba Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12

Datasheet Download

Link URL