DA9155M

2.5 A Companion Charger for rapid charging

10.2.1

Register map paging

The 2-wire interface has direct access to two pages of the register map (up to 256 addresses). The

register at address zero on each page is used as a page control register (the LSB of the PAGE

register is ignored). Writing to the page control register changes the active page for all subsequent

read/write operations unless an automatic return to page 0 was selected by asserting the REVERT

register.

Alternatively, DA9155M offers a way to access register pages which avoids changing the active page

via the PAGE register. DA9155M can respond to multiple consecutive slave addresses and update

the PAGE register automatically based on the slave address. For example, when IF_BASE_ADDR =

0x58, the PAGE register responds to the slave address as follows:

Slave address = 0x58

 PAGE = 0x00

Slave address = 0x59

 PAGE = 0x02

Slave address = 0x5A

 PAGE = 0x04

Slave address = 0x5B

 PAGE = 0x06

The consecutive addresses are obtained by replacing the two LSB in IF_BASE_ADDR with “00”,

“01”, “10”, or “11”. This feature can be enabled in the I2C_EXTEND_EN register.

10.2.2

Details of the 2-wire protocol

All data is transmitted across the 2-wire bus in 8-bit groups. To send a bit the SDA line is driven at

the intended state while the SCL is low. Once the SDA has settled, the SCL line is brought high and

then low. This pulse on SCL clocks the SDA bit into the receiver’s shift register.

A two-byte serial protocol is used containing one address byte and one data byte. Data and address

transfer is transmitted MSB first for both read and write operations. All transmission begins with the

START condition from the master during which the bus is in IDLE state (the bus is free). It is initiated

by a high-to-low transition on the SDA line while the SCL is in the high state. A STOP condition is

indicated by a low-to-high transition on the SDA line while the SCL is in the high state. The START

and STOP conditions are illustrated in Figure 12.

START

STOP

SDA

SCL

Transaction

Figure 12: Timing of the START and STOP conditions

The 2-wire bus will be monitored by DA9155M for a valid slave address whenever the interface is

enabled. It responds immediately when it receives its own slave address. This is acknowledged by

pulling the SDA line low during the following clock cycle (white blocks marked with ‘A’ in the following

figures).

The protocol for a register write from master to slave consists of a START condition, a slave address,

a read/write-bit, 8-bit address, 8-bit data, and a STOP condition. DA9155M responds to all bytes with

an ACK. A register write operation is illustrated in Figure 13.

Datasheet

v3.05

22-July-2016

CFR0011-120-00 Rev 5

18 of 36

© 2016 Dialog Semiconductor