IW7023 datasheet(21/35 Pages) DIALOG

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iW7023

16-Channel LED Driver for LCD Panel Backlighting

Rev. 1.0

iW7023

Datasheet

21 of 35

Definition

Access

Description

Real-Time Update Control Registers (User Operation Mode Based) (cont.)

scan_duty[4:0]

R/W

0: 20%

1: 24%

…..

5: 40% (default)

…..

20: 100% (Any number greater than this results in 100%)

This Scanning Mode dimming ratio may be slightly adjusted by the IC internally

in order to meet the requirement of Tsc being the integer number of the dimming

period (please refer to the Scanning mode timing diagram).

Please note that for thermal reasons, it is not recommended in most cases to use

more than 50% scan duty unless the scan duty SISET value is not set higher than

the Local Dimming (LD) current setting.

pwm_freq[4:0]

R/W

If TV is in NTSC mode:

5-bit PWM dimming frequency setting, adjusting frequency in 20 steps

0 - 19: 120Hz to 2.4kHz with 120Hz per step for 10-bit PWM resolution

0 - 3: 120Hz to 480Hz with 120Hz per step for 12-bit PWM resolution

If TV is in PAL mode:

5-bit PWM dimming frequency setting, adjusting frequency in 24 steps

0 - 23: 100Hz to 2.4kHz with 100Hz per step for 10-bit PWM resolution

0 - 3: 100Hz to 480Hz with 100Hz per step for 12-bit PWM resolution

In TV is in 3D game mode:

5-bit PWM dimming frequency setting, adjusting frequency in 25 steps

0 - 24: 96Hz to 2.4kHz with 96Hz per step for 10-bit PWM resolution

0 - 3: 96Hz to 480Hz with 96Hz per step for 12-bit PWM resolution

The default value is 0

soft_rst

R/W

0: no action (default)

1: perform soft reset,

- all the IC internal registers in synclk clock domain are reset;

- all the IC internal registers in sck clock domain remain in the same

configuration

sw_init_byp

R/W

0: software needs to initialize the One Time registers and User mode before IC

start to calibration (default)

1: bypass software initialization step

pwm_bnk_cfg[1:0]

R/W

0: PWM sampling blank time is 8 clock cycles from the rising edge of PWM

1: PWM sampling blank time is 32 clock cycles from the rising edge of PWM

(default)

2: PWM sampling blank time is 128 clock cycles from the rising edge of PWM

3: PWM sampling blank time is 254 clock cycles from the rising edge of PWM

dis_open_prot

R/W

0: enable OPEN protection (default)

1: disable OPEN protection

12.2 Control Register Bit Field Definitions (cont.)

IW7023 Datasheet(PDF) 21 Page - Dialog Semiconductor

IW7023 Datasheet(HTML) 21 Page - Dialog Semiconductor

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