AS4C4M16SA datasheet(11/54 Pages) ALSC

11 / 54 page

AS4C4M16SA - Automotive

Confidential

Rev. 1.0-63nm Mar. /2014

The BankPrecharge/PrechargeAll command that interrupts a write burst without the auto precharge function

should be issued m cycles after the clock edge in which the last data-in element is registered, where m equals

tWR/tCK rounded up to the next whole number. In addition, the DQM signals must be used to mask input data,

starting with the clock edge following the last data-in element and ending with the clock edge on which the

BankPrecharge/PrechargeAll command is entered (refer to the following figure).

CLK

COMMAND

WRITE

NOP

Precharge

NOP

Activate

NOP

DQM

Don’t Care

ADDRESS

Bank

Col n

Bank (s)

ROW

tRP

DIN

N+1

tWR

Note: The LDQM/UDQM can remain low in this example if the length of the write burst is 1 or 2.

Figure 13. Write to Precharge

Write and AutoPrecharge command

(RAS# = "H", CAS# = "L", WE# = "L", BAs = Bank, A10 = "H", A0-A7 = Column Address)

The Write and AutoPrecharge command performs the precharge operation automatically after the write

operation. Once this command is given, any subsequent command can not occur within a time delay of

{(burst length -1) + tWR + tRP(min.)}. At full-page burst, only the write operation is performed in this

command and the auto precharge function is ignored.

CLK

DIN A0

DIN A1

COMMAND

Bank A

Activate

NOP

WRITE A

Auto Precharge

NOP

Bank A

Activate

tDAL=tWR+tRP

tDAL

Begin AutoPrecharge

Bank can be reactivated at

completion of tDAL

Figure 14. Burst Write with Auto-Precharge (Burst Length = 2)

Mode Register Set command (RAS# = "L", CAS# = "L", WE# = "L", A0-A11 = Register Data)

The mode register stores the data for controlling the various operating modes of SDRAM. The Mode

Mode register to make SDRAM useful for a variety of different applications. The default values of the

Mode Register after power-up are undefined; therefore this command must be issued at the power-up

sequence. The state of pins A0~A9 and A11 in the same cycle is the data written to the mode register.

Two clock cycles are required to complete the write in the mode register (refer to the following figure). The

contents of the mode register can be changed using the same command and the clock cycle

requirements during operation as long as all banks are in the idle state.

AS4C4M16SA Datasheet(PDF) 11 Page - Alliance Semiconductor Corporation

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