MCP9902 datasheet(6/50 Pages) MICROCHIP

6 / 50 page

MCP9902/3/4

DS20005382C-page 6

 2015-2016 Microchip Technology Inc.

FIGURE 1-2:

SMBus Timing Diagram.

1.4

SMBUS Module Specifications

Operating Conditions

(unless otherwise indicated): 3.0V ≤ VDD ≤ 3.6V at -40°C ≤ TA ≤ +85°C

Characteristic

Sym.

Min.

Typ.

Max.

Units

Conditions

SMBus Interface

Input High Voltage

VIH

2.1

—

VDD

V—

Input Low Voltage

VIL

-0.3

0.8

—

Leakage Current

ILEAK

—

±5

µA

Powered or unpowered

TA < +85°C

Hysteresis

—

0.1

 VDD

—mV

—

Input Capacitance

CIN

—5

—

Output Low Sink Current

IOL

8.2

—

SMDATA = 0.2V

SMBus Timing

Clock Frequency

fSMB

—

400

kHz

—

Spike Suppression

tSP

—

Bus Free Time Stop to

Start

tBUF

1.3

—

µs

—

Hold Time: Start

tHD:STA

0.6

—

µs

—

Setup Time: Start

tSU:STA

0.6

—

µs

—

Setup Time: Stop

tSU:STO

0.6

—

µs

—

Data Hold Time

tHD:DAT

0—

—

µs

—

Data Hold Time

tHD:DAT

0.3

—

µs

When transmitting to the master

Data Setup Time

tSU:DAT

100

—

When receiving from the master

Clock Low Period

tLOW

1.3

—

µs

—

Clock High Period

tHIGH

0.6

—

µs

—

Clock/Data Fall Time

tFALL

——

300

—

Clock/Data Rise Time

tRISE

—

300

Min = 20+0.1 CLOAD ns

Capacitive Load

CLOAD

—

400

Min = 20+0.1 CLOAD ns

Timeout

tTIME-

OUT

—

Per bus line

Clock Frequency

fSMB

—

400

kHz

Disabled by default

SMDATA

SMCLK

BUF

S - Start Condition

P - Stop Condition

T HIGH

T LOW

HD:STA

SU:STO

HD:STA

HD:DAT

SU:DAT

SU:STA

FALL

RISE

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