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E981.07 Datasheet(PDF) 21 Page - ELMOS Semiconductor AG |
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E981.07 Datasheet(HTML) 21 Page - ELMOS Semiconductor AG |
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21 / 46 page ![]() E981.07 Two Channel Sensor Interface PSI5 ADVANCE PRODUCT INFORMATION JUL 26, 2011 5.1.5 Current Limitation The circuit provides an over current protection of the RSU interfaces. When the current measured by the current comparator exceeds typically 100 mA, the error flag HE is set and the voltage will be turned off after a delay Tsat_oc_del_xx. To allow “in-rush” current when the channel is turned ON the error condition is masked for Tsat_oc_sdel_xx. During this delay, the HE-bit is not set. (xx refers to supply mode: “standard” or “increased”: refer to §4.2.1-1a,1b, 2a, 2b) 5.1.6 Over Voltage Protection The RSU interfaces are voltage protected against 40V. When the output voltage increases to 0.5V above the nominal voltage, a pull down current is activated ( see 4. 1.12.3) . When the current reaches the specified limit the error flag OE is set and the voltage will be turned off after a delay Tsat_oc_odel_ls. If a short to V+ occurs prior to the channel activation the error condition is masked for a delay Tsat_oc_sdel_xx). During this delay the OE bit is not set. (xx refers to supply-mode: “standard” or “increased”: refer to §4.2.1, 1a, .1b, 3) 5.1.7 Synchronous Parallel Bus Mode (PSI5-P10P-500/3L) In parallel bus mode application, the sensors are connected in parallel to the bus line like shown in Figure 5.1-4. It is possible to connect up to three sensor to each channel of the 981.07. The sync cycle time is 500μs with a data transmission rate of 125kbit/s. The synchronisation pulse for the satellite channel feeds SATFD1-SATFD2 can be activated by MCU via the SAT_SYNC pin of the device. When a rising edge is detected, the 981.07 outputs sync pulses on channels SATFD1-SATFD2 in sequence to reduce the average current inrush to the satellites as shown in Figure 5.1-5. The satellites can transmit from one to three messages per sync pulse received. The Figure 5.1-6 shows the timing for one channel. Figure 5.1-4 Synchronous Parallel Bus Mode Configuration (PSI5-P10P-500/3L) In order to avoid EMC problems, the synchronisations pulses of the satellites will not be performed at the same time, but consecutively like it is shown in the figure below. ELMOS Semiconductor AG Data Sheet 21 / 45 QM-No.: 25DS0050E.00 This document contains information on a new product. ELMOS Semiconductor AG reserves the right to change specifications and information herein without notice. V SAT_OUT_OP t GND S2 S1 S3 MCU 981.07 SPI V SAT_OUT_X S3 V SAT_OUT_SYNC V SAT_OUT_X T SYNC S1 S2 SAT_SYNC |
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